From aeb1ba84718d970ff43b2775aa9019357c24a90c Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 18 Jan 2017 15:22:33 -0600 Subject: [PATCH] gateware: use default MiSoC timer --- artiq/gateware/soc.py | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/artiq/gateware/soc.py b/artiq/gateware/soc.py index 0be283570..d30976ebc 100644 --- a/artiq/gateware/soc.py +++ b/artiq/gateware/soc.py @@ -10,19 +10,13 @@ from artiq import __artiq_dir__ as artiq_dir class AMPSoC: - """Contains timer, kernel CPU and mailbox for ARTIQ SoCs. + """Contains kernel CPU and mailbox for ARTIQ SoCs. - Users must disable the timer from the platform SoC and provide - a "mailbox" entry in the memory map. + Users must provide a "mailbox" entry in the memory map. """ def __init__(self): if not hasattr(self, "cpu"): raise ValueError("Platform SoC must be initialized first") - if hasattr(self, "timer0"): - raise ValueError("Timer already exists. " - "Initialize platform SoC using with_timer=False") - - self.submodules.timer0 = timer.Timer(width=64) self.submodules.kernel_cpu = amp.KernelCPU(self.platform) self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)