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siphaser: minor cleanup

This commit is contained in:
Sebastien Bourdeauducq 2018-03-07 10:04:18 +08:00
parent e6e5236ce2
commit acfd9db185
1 changed files with 10 additions and 6 deletions
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16
artiq/gateware/drtio/si_phaser.py
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@ -18,7 +18,7 @@ class SiPhaser7Series(Module, AutoCSR):
# we do not use the crystal reference so that the PFD (f3) frequency # we do not use the crystal reference so that the PFD (f3) frequency
# can be high. # can be high.
mmcm_freerun_fb = Signal() mmcm_freerun_fb = Signal()
self.mmcm_freerun_output = Signal() mmcm_freerun_output = Signal()
self.specials += \ self.specials += \
Instance("MMCME2_BASE", Instance("MMCME2_BASE",
p_CLKIN1_PERIOD=1e9/125e6, p_CLKIN1_PERIOD=1e9/125e6,
@ -29,14 +29,14 @@ class SiPhaser7Series(Module, AutoCSR):
o_CLKFBOUT=mmcm_freerun_fb, i_CLKFBIN=mmcm_freerun_fb, o_CLKFBOUT=mmcm_freerun_fb, i_CLKFBIN=mmcm_freerun_fb,
p_CLKOUT0_DIVIDE_F=5.0, o_CLKOUT0=self.mmcm_freerun_output, p_CLKOUT0_DIVIDE_F=5.0, o_CLKOUT0=mmcm_freerun_output,
) )
# 150MHz to 150MHz with controllable phase shift, VCO @ 1200MHz. # 150MHz to 150MHz with controllable phase shift, VCO @ 1200MHz.
# Inserted between CDR and output to Si, used to correct # Inserted between CDR and output to Si, used to correct
# non-determinstic skew of Si5324. # non-determinstic skew of Si5324.
mmcm_ps_fb = Signal() mmcm_ps_fb = Signal()
self.mmcm_ps_output = Signal() mmcm_ps_output = Signal()
self.specials += \ self.specials += \
Instance("MMCME2_ADV", Instance("MMCME2_ADV",
p_CLKIN1_PERIOD=1e9/150e6, p_CLKIN1_PERIOD=1e9/150e6,
@ -51,7 +51,7 @@ class SiPhaser7Series(Module, AutoCSR):
o_CLKFBOUT=mmcm_ps_fb, i_CLKFBIN=mmcm_ps_fb, o_CLKFBOUT=mmcm_ps_fb, i_CLKFBIN=mmcm_ps_fb,
p_CLKOUT0_USE_FINE_PS="TRUE", p_CLKOUT0_USE_FINE_PS="TRUE",
o_CLKOUT0=self.mmcm_ps_output, o_CLKOUT0=mmcm_ps_output,
i_PSCLK=ClockSignal(), i_PSCLK=ClockSignal(),
i_PSEN=self.phase_shift.re, i_PSEN=self.phase_shift.re,
@ -62,8 +62,8 @@ class SiPhaser7Series(Module, AutoCSR):
si5324_clkin_se = Signal() si5324_clkin_se = Signal()
self.specials += [ self.specials += [
Instance("BUFGMUX", Instance("BUFGMUX",
i_I0=self.mmcm_freerun_output, i_I0=mmcm_freerun_output,
i_I1=self.mmcm_ps_output, i_I1=mmcm_ps_output,
i_S=self.switch_clocks.storage, i_S=self.switch_clocks.storage,
o_O=si5324_clkin_se o_O=si5324_clkin_se
), ),
@ -83,3 +83,7 @@ class SiPhaser7Series(Module, AutoCSR):
clkout_sample1 = Signal() # IOB register clkout_sample1 = Signal() # IOB register
self.sync.rtio_rx0 += clkout_sample1.eq(si5324_clkout_se) self.sync.rtio_rx0 += clkout_sample1.eq(si5324_clkout_se)
self.specials += MultiReg(clkout_sample1, self.sample_result.status) self.specials += MultiReg(clkout_sample1, self.sample_result.status)
# expose MMCM outputs - used for clock constraints
self.mmcm_freerun_output = mmcm_freerun_output
self.mmcm_ps_output = mmcm_ps_output