From acfd9db185aa29238f282aee61ac357857a208e8 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 7 Mar 2018 10:04:18 +0800
Subject: [PATCH] siphaser: minor cleanup

---
 artiq/gateware/drtio/si_phaser.py | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/artiq/gateware/drtio/si_phaser.py b/artiq/gateware/drtio/si_phaser.py
index 54c9af2fb..b4681615b 100644
--- a/artiq/gateware/drtio/si_phaser.py
+++ b/artiq/gateware/drtio/si_phaser.py
@@ -18,7 +18,7 @@ class SiPhaser7Series(Module, AutoCSR):
         # we do not use the crystal reference so that the PFD (f3) frequency
         # can be high.
         mmcm_freerun_fb = Signal()
-        self.mmcm_freerun_output = Signal()
+        mmcm_freerun_output = Signal()
         self.specials += \
             Instance("MMCME2_BASE",
                 p_CLKIN1_PERIOD=1e9/125e6,
@@ -29,14 +29,14 @@ class SiPhaser7Series(Module, AutoCSR):
 
                 o_CLKFBOUT=mmcm_freerun_fb, i_CLKFBIN=mmcm_freerun_fb,
 
-                p_CLKOUT0_DIVIDE_F=5.0, o_CLKOUT0=self.mmcm_freerun_output,
+                p_CLKOUT0_DIVIDE_F=5.0, o_CLKOUT0=mmcm_freerun_output,
             )
         
         # 150MHz to 150MHz with controllable phase shift, VCO @ 1200MHz.
         # Inserted between CDR and output to Si, used to correct 
         # non-determinstic skew of Si5324.
         mmcm_ps_fb = Signal()
-        self.mmcm_ps_output = Signal()
+        mmcm_ps_output = Signal()
         self.specials += \
             Instance("MMCME2_ADV",
                 p_CLKIN1_PERIOD=1e9/150e6,
@@ -51,7 +51,7 @@ class SiPhaser7Series(Module, AutoCSR):
                 o_CLKFBOUT=mmcm_ps_fb, i_CLKFBIN=mmcm_ps_fb,
 
                 p_CLKOUT0_USE_FINE_PS="TRUE",
-                o_CLKOUT0=self.mmcm_ps_output,
+                o_CLKOUT0=mmcm_ps_output,
 
                 i_PSCLK=ClockSignal(),
                 i_PSEN=self.phase_shift.re,
@@ -62,8 +62,8 @@ class SiPhaser7Series(Module, AutoCSR):
         si5324_clkin_se = Signal()
         self.specials += [
             Instance("BUFGMUX",
-                i_I0=self.mmcm_freerun_output,
-                i_I1=self.mmcm_ps_output,
+                i_I0=mmcm_freerun_output,
+                i_I1=mmcm_ps_output,
                 i_S=self.switch_clocks.storage,
                 o_O=si5324_clkin_se
             ),
@@ -83,3 +83,7 @@ class SiPhaser7Series(Module, AutoCSR):
         clkout_sample1 = Signal()  # IOB register
         self.sync.rtio_rx0 += clkout_sample1.eq(si5324_clkout_se)
         self.specials += MultiReg(clkout_sample1, self.sample_result.status)
+
+        # expose MMCM outputs - used for clock constraints
+        self.mmcm_freerun_output = mmcm_freerun_output
+        self.mmcm_ps_output = mmcm_ps_output