forked from M-Labs/artiq
siphaser: minor cleanup
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e6e5236ce2
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acfd9db185
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@ -18,7 +18,7 @@ class SiPhaser7Series(Module, AutoCSR):
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# we do not use the crystal reference so that the PFD (f3) frequency
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# we do not use the crystal reference so that the PFD (f3) frequency
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# can be high.
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# can be high.
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mmcm_freerun_fb = Signal()
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mmcm_freerun_fb = Signal()
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self.mmcm_freerun_output = Signal()
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mmcm_freerun_output = Signal()
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self.specials += \
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self.specials += \
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Instance("MMCME2_BASE",
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Instance("MMCME2_BASE",
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p_CLKIN1_PERIOD=1e9/125e6,
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p_CLKIN1_PERIOD=1e9/125e6,
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@ -29,14 +29,14 @@ class SiPhaser7Series(Module, AutoCSR):
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o_CLKFBOUT=mmcm_freerun_fb, i_CLKFBIN=mmcm_freerun_fb,
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o_CLKFBOUT=mmcm_freerun_fb, i_CLKFBIN=mmcm_freerun_fb,
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p_CLKOUT0_DIVIDE_F=5.0, o_CLKOUT0=self.mmcm_freerun_output,
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p_CLKOUT0_DIVIDE_F=5.0, o_CLKOUT0=mmcm_freerun_output,
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)
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)
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# 150MHz to 150MHz with controllable phase shift, VCO @ 1200MHz.
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# 150MHz to 150MHz with controllable phase shift, VCO @ 1200MHz.
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# Inserted between CDR and output to Si, used to correct
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# Inserted between CDR and output to Si, used to correct
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# non-determinstic skew of Si5324.
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# non-determinstic skew of Si5324.
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mmcm_ps_fb = Signal()
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mmcm_ps_fb = Signal()
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self.mmcm_ps_output = Signal()
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mmcm_ps_output = Signal()
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self.specials += \
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self.specials += \
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Instance("MMCME2_ADV",
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Instance("MMCME2_ADV",
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p_CLKIN1_PERIOD=1e9/150e6,
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p_CLKIN1_PERIOD=1e9/150e6,
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@ -51,7 +51,7 @@ class SiPhaser7Series(Module, AutoCSR):
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o_CLKFBOUT=mmcm_ps_fb, i_CLKFBIN=mmcm_ps_fb,
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o_CLKFBOUT=mmcm_ps_fb, i_CLKFBIN=mmcm_ps_fb,
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p_CLKOUT0_USE_FINE_PS="TRUE",
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p_CLKOUT0_USE_FINE_PS="TRUE",
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o_CLKOUT0=self.mmcm_ps_output,
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o_CLKOUT0=mmcm_ps_output,
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i_PSCLK=ClockSignal(),
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i_PSCLK=ClockSignal(),
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i_PSEN=self.phase_shift.re,
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i_PSEN=self.phase_shift.re,
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@ -62,8 +62,8 @@ class SiPhaser7Series(Module, AutoCSR):
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si5324_clkin_se = Signal()
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si5324_clkin_se = Signal()
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self.specials += [
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self.specials += [
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Instance("BUFGMUX",
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Instance("BUFGMUX",
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i_I0=self.mmcm_freerun_output,
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i_I0=mmcm_freerun_output,
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i_I1=self.mmcm_ps_output,
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i_I1=mmcm_ps_output,
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i_S=self.switch_clocks.storage,
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i_S=self.switch_clocks.storage,
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o_O=si5324_clkin_se
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o_O=si5324_clkin_se
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),
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),
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@ -83,3 +83,7 @@ class SiPhaser7Series(Module, AutoCSR):
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clkout_sample1 = Signal() # IOB register
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clkout_sample1 = Signal() # IOB register
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self.sync.rtio_rx0 += clkout_sample1.eq(si5324_clkout_se)
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self.sync.rtio_rx0 += clkout_sample1.eq(si5324_clkout_se)
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self.specials += MultiReg(clkout_sample1, self.sample_result.status)
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self.specials += MultiReg(clkout_sample1, self.sample_result.status)
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# expose MMCM outputs - used for clock constraints
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self.mmcm_freerun_output = mmcm_freerun_output
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self.mmcm_ps_output = mmcm_ps_output
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