forked from M-Labs/artiq
slave_fpga: check DONE before loading
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abd160d143
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@ -39,17 +39,20 @@ pub fn load() -> Result<(), &'static str> {
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info!("Slave FPGA gateware length: 0x{:06x}", length);
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info!("Slave FPGA gateware length: 0x{:06x}", length);
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unsafe {
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unsafe {
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csr::slave_fpga_cfg::oe_write(CCLK_BIT | DIN_BIT | PROGRAM_B_BIT);
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if csr::slave_fpga_cfg::in_read() & DONE_BIT != 0 {
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info!("Slave FPGA is DONE before loading");
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}
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csr::slave_fpga_cfg::out_write(0);
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csr::slave_fpga_cfg::out_write(0);
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csr::slave_fpga_cfg::oe_write(CCLK_BIT | DIN_BIT | PROGRAM_B_BIT);
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clock::spin_us(1_000); // TPROGRAM=250ns min, be_generous
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clock::spin_us(1_000); // TPROGRAM=250ns min, be_generous
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if csr::slave_fpga_cfg::in_read() & INIT_B_BIT != 0 {
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if csr::slave_fpga_cfg::in_read() & INIT_B_BIT != 0 {
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return Err("Slave FPGA did not react to PROGRAM.");
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return Err("Slave FPGA did not react to PROGRAM.");
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}
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}
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csr::slave_fpga_cfg::out_write(PROGRAM_B_BIT);
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csr::slave_fpga_cfg::out_write(PROGRAM_B_BIT);
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clock::spin_us(5_000); // TPL=5ms max
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clock::spin_us(10_000); // TPL=5ms max
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if csr::slave_fpga_cfg::in_read() & INIT_B_BIT == 0 {
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if csr::slave_fpga_cfg::in_read() & INIT_B_BIT == 0 {
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return Err("Slave FPGA did finish INITialization.");
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return Err("Slave FPGA did not finish INITialization.");
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}
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}
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for i in slice::from_raw_parts(GATEWARE.offset(8), length) {
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for i in slice::from_raw_parts(GATEWARE.offset(8), length) {
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