forked from M-Labs/artiq
firmware: move wait for write completion to read()
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a6ae08d8b8
commit
a04a36ee36
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@ -22,13 +22,13 @@ fn write(addr: u16, data: u8) {
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::data_write(
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((addr as u32) << 16) | ((data as u32) << 8));
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while csr::converter_spi::writable_read() == 0 {}
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}
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}
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fn read(addr: u16) -> u8 {
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unsafe {
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write((1 << 15) | addr, 0);
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::data_read() as u8
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}
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}
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@ -78,7 +78,6 @@ mod hmc830 {
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unsafe {
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::data_write(val << 1); // last clk cycle loads data
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while csr::converter_spi::writable_read() == 0 {}
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}
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}
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@ -88,6 +87,7 @@ mod hmc830 {
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// the SPI round trip delay and stick with CPHA=0
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write((1 << 6) | addr, 0);
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unsafe {
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::data_read() & 0xffffff
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}
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}
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@ -173,7 +173,6 @@ mod hmc7043 {
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unsafe {
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::data_write(val << 8);
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while csr::converter_spi::writable_read() == 0 {}
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}
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}
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@ -7,7 +7,7 @@ mod imp {
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return Err(())
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}
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unsafe {
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while csr::converter_spi::idle_read() == 0 {}
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::offline_write(flags >> 0 & 1);
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csr::converter_spi::end_write(flags >> 1 & 1);
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// input (in RTIO): flags >> 2 & 1
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@ -38,7 +38,6 @@ mod imp {
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unsafe {
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::data_write(data);
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while csr::converter_spi::writable_read() == 0 {}
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}
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Ok(())
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}
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@ -48,6 +47,7 @@ mod imp {
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return Err(())
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}
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Ok(unsafe {
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::data_read()
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})
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}
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