forked from M-Labs/artiq
gateware/spi: style
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@ -174,8 +174,8 @@ class AD5360:
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self.bus.ref_period_mu) -
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3*self.bus.ref_period_mu -
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self.core.seconds_to_mu(1.5*us))
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for i in range(len(values)):
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self.write_channel(i, values[i], op)
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for i, value in enumerate(values):
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self.write_channel(i, value, op)
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delay_mu(3*self.bus.ref_period_mu + # latency alignment ttl to spi
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self.core.seconds_to_mu(1.5*us)) # t10 max busy low for one channel
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self.load()
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@ -15,7 +15,7 @@ from artiq.coredevice.rtio import rtio_output, rtio_input_data
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__all__ = [
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"SPI_DATA_ADDR", "SPI_XFER_ADDR", "SPI_CONFIG_ADDR",
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"SPI_DATA_ADDR", "SPI_XFER_ADDR", "SPI_CONFIG_ADDR",
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"SPI_OFFLINE", "SPI_ACTIVE", "SPI_PENDING",
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"SPI_CS_POLARITY", "SPI_CLK_POLARITY", "SPI_CLK_PHASE",
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"SPI_LSB_FIRST", "SPI_HALF_DUPLEX",
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