From a9798ae2b16e39a89e29e15dac957d349183ea26 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 23 Oct 2017 18:45:53 +0800 Subject: [PATCH] gateware/spi: style --- artiq/coredevice/ad5360.py | 4 ++-- artiq/coredevice/spi.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/coredevice/ad5360.py b/artiq/coredevice/ad5360.py index c470fbec2..aac70c962 100644 --- a/artiq/coredevice/ad5360.py +++ b/artiq/coredevice/ad5360.py @@ -174,8 +174,8 @@ class AD5360: self.bus.ref_period_mu) - 3*self.bus.ref_period_mu - self.core.seconds_to_mu(1.5*us)) - for i in range(len(values)): - self.write_channel(i, values[i], op) + for i, value in enumerate(values): + self.write_channel(i, value, op) delay_mu(3*self.bus.ref_period_mu + # latency alignment ttl to spi self.core.seconds_to_mu(1.5*us)) # t10 max busy low for one channel self.load() diff --git a/artiq/coredevice/spi.py b/artiq/coredevice/spi.py index f9c47f5e7..22859a962 100644 --- a/artiq/coredevice/spi.py +++ b/artiq/coredevice/spi.py @@ -15,7 +15,7 @@ from artiq.coredevice.rtio import rtio_output, rtio_input_data __all__ = [ - "SPI_DATA_ADDR", "SPI_XFER_ADDR", "SPI_CONFIG_ADDR", + "SPI_DATA_ADDR", "SPI_XFER_ADDR", "SPI_CONFIG_ADDR", "SPI_OFFLINE", "SPI_ACTIVE", "SPI_PENDING", "SPI_CS_POLARITY", "SPI_CLK_POLARITY", "SPI_CLK_PHASE", "SPI_LSB_FIRST", "SPI_HALF_DUPLEX",