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gateware/soc: factor code to connect CSR device to kernel CPU

This commit is contained in:
Sebastien Bourdeauducq 2016-03-03 15:12:15 +08:00
parent b662a6fcbd
commit a901971e58
3 changed files with 17 additions and 25 deletions
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22
artiq/gateware/soc.py
View File

@ -32,11 +32,17 @@ class AMPSoC:
self.mem_map["mailbox"] | 0x80000000, 4) self.mem_map["mailbox"] | 0x80000000, 4)
self.submodules.timer_kernel = timer.Timer() self.submodules.timer_kernel = timer.Timer()
timer_csrs = self.timer_kernel.get_csrs() self.register_kernel_cpu_csrdevice("timer_kernel")
timerwb = wishbone.CSRBank(timer_csrs)
self.submodules += timerwb def register_kernel_cpu_csrdevice(self, name):
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["timer_kernel"]), # make sure the device is not getting connected to the comms-CPU already
timerwb.bus) assert self.csr_map[name] is None
self.add_csr_region("timer_kernel",
self.mem_map["timer_kernel"] | 0x80000000, 32, csrs = getattr(self, name).get_csrs()
timer_csrs) bank = wishbone.CSRBank(csrs)
self.submodules += bank
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map[name]),
bank.bus)
self.add_csr_region(name,
self.mem_map[name] | 0x80000000, 32,
csrs)

8
artiq/gateware/targets/kc705.py
View File

@ -134,6 +134,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
def add_rtio(self, rtio_channels): def add_rtio(self, rtio_channels):
self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk) self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
self.submodules.rtio = rtio.RTIO(rtio_channels) self.submodules.rtio = rtio.RTIO(rtio_channels)
self.register_kernel_cpu_csrdevice("rtio")
self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
@ -154,13 +155,6 @@ class _NIST_Ions(MiniSoC, AMPSoC):
self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk) self.ethphy.crg.cd_eth_tx.clk)
rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wishbone.CSRBank(rtio_csrs)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
self.rtiowb.bus)
self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
rtio_csrs)
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio, self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
self.get_native_sdram_if()) self.get_native_sdram_if())

12
artiq/gateware/targets/pipistrello.py
View File

@ -209,20 +209,12 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel()) rtio_channels.append(rtio.LogChannel())
# RTIO core # RTIO logic
self.submodules.rtio = rtio.RTIO(rtio_channels) self.submodules.rtio = rtio.RTIO(rtio_channels)
self.register_kernel_cpu_csrdevice("rtio")
self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
# CPU connections
rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wishbone.CSRBank(rtio_csrs)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
self.rtiowb.bus)
self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
rtio_csrs)
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio, self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
self.get_native_sdram_if()) self.get_native_sdram_if())