From a901971e58d3995d1df283c9e1e946e6205ea700 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 3 Mar 2016 15:12:15 +0800
Subject: [PATCH] gateware/soc: factor code to connect CSR device to kernel CPU

---
 artiq/gateware/soc.py                 | 22 ++++++++++++++--------
 artiq/gateware/targets/kc705.py       |  8 +-------
 artiq/gateware/targets/pipistrello.py | 12 ++----------
 3 files changed, 17 insertions(+), 25 deletions(-)

diff --git a/artiq/gateware/soc.py b/artiq/gateware/soc.py
index e97faa0e5..908701ad2 100644
--- a/artiq/gateware/soc.py
+++ b/artiq/gateware/soc.py
@@ -32,11 +32,17 @@ class AMPSoC:
                                self.mem_map["mailbox"] | 0x80000000, 4)
 
         self.submodules.timer_kernel = timer.Timer()
-        timer_csrs = self.timer_kernel.get_csrs()
-        timerwb = wishbone.CSRBank(timer_csrs)
-        self.submodules += timerwb
-        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["timer_kernel"]),
-                                     timerwb.bus)
-        self.add_csr_region("timer_kernel",
-                            self.mem_map["timer_kernel"] | 0x80000000, 32,
-                            timer_csrs)
+        self.register_kernel_cpu_csrdevice("timer_kernel")
+
+    def register_kernel_cpu_csrdevice(self, name):
+        # make sure the device is not getting connected to the comms-CPU already
+        assert self.csr_map[name] is None
+
+        csrs = getattr(self, name).get_csrs()
+        bank = wishbone.CSRBank(csrs)
+        self.submodules += bank
+        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map[name]),
+                                     bank.bus)
+        self.add_csr_region(name,
+                            self.mem_map[name] | 0x80000000, 32,
+                            csrs)
diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
index 5854bee17..e7268d3d0 100755
--- a/artiq/gateware/targets/kc705.py
+++ b/artiq/gateware/targets/kc705.py
@@ -134,6 +134,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
     def add_rtio(self, rtio_channels):
         self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
         self.submodules.rtio = rtio.RTIO(rtio_channels)
+        self.register_kernel_cpu_csrdevice("rtio")
         self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
         self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
 
@@ -154,13 +155,6 @@ class _NIST_Ions(MiniSoC, AMPSoC):
             self.ethphy.crg.cd_eth_rx.clk,
             self.ethphy.crg.cd_eth_tx.clk)
 
-        rtio_csrs = self.rtio.get_csrs()
-        self.submodules.rtiowb = wishbone.CSRBank(rtio_csrs)
-        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
-                                     self.rtiowb.bus)
-        self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
-                            rtio_csrs)
-
         self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
             self.get_native_sdram_if())
 
diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py
index 655ec22b7..ed1966e33 100755
--- a/artiq/gateware/targets/pipistrello.py
+++ b/artiq/gateware/targets/pipistrello.py
@@ -209,20 +209,12 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
         self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
         rtio_channels.append(rtio.LogChannel())
 
-        # RTIO core
+        # RTIO logic
         self.submodules.rtio = rtio.RTIO(rtio_channels)
+        self.register_kernel_cpu_csrdevice("rtio")
         self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
         self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width
         self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
-
-        # CPU connections
-        rtio_csrs = self.rtio.get_csrs()
-        self.submodules.rtiowb = wishbone.CSRBank(rtio_csrs)
-        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
-                                     self.rtiowb.bus)
-        self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
-                            rtio_csrs)
-
         self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
             self.get_native_sdram_if())