srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

RTIO: use TS counter in the correct CD 

artiq/m-labs#938
This commit is contained in:
Robert Jördens 2018-03-07 11:26:01 +00:00
parent 8b70db5f17
commit a6d1b030c1
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/gateware/rtio/core.py
View File

@ -67,7 +67,7 @@ class Core(Module, AutoCSR):
coarse_ts = Signal(64-glbl_fine_ts_width) coarse_ts = Signal(64-glbl_fine_ts_width)
self.sync.rtio += coarse_ts.eq(coarse_ts + 1) self.sync.rtio += coarse_ts.eq(coarse_ts + 1)
coarse_ts_cdc = GrayCodeTransfer(len(coarse_ts)) coarse_ts_cdc = GrayCodeTransfer(len(coarse_ts)) # from rtio to sys
self.submodules += coarse_ts_cdc self.submodules += coarse_ts_cdc
self.comb += [ self.comb += [
coarse_ts_cdc.i.eq(coarse_ts), coarse_ts_cdc.i.eq(coarse_ts),
@ -83,7 +83,7 @@ class Core(Module, AutoCSR):
interface=self.cri) interface=self.cri)
self.submodules += outputs self.submodules += outputs
self.comb += outputs.coarse_timestamp.eq(coarse_ts) self.comb += outputs.coarse_timestamp.eq(coarse_ts)
self.sync += outputs.minimum_coarse_timestamp.eq(coarse_ts + 16) self.sync += outputs.minimum_coarse_timestamp.eq(coarse_ts_cdc.o + 16)
inputs = InputCollector(channels, glbl_fine_ts_width, "async", inputs = InputCollector(channels, glbl_fine_ts_width, "async",
quash_channels=quash_channels, quash_channels=quash_channels,