From a6d1b030c1f1697755a081f671c571d734a96187 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Wed, 7 Mar 2018 11:26:01 +0000 Subject: [PATCH] RTIO: use TS counter in the correct CD artiq/m-labs#938 --- artiq/gateware/rtio/core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/rtio/core.py b/artiq/gateware/rtio/core.py index c2bee2947..484c64bbe 100644 --- a/artiq/gateware/rtio/core.py +++ b/artiq/gateware/rtio/core.py @@ -67,7 +67,7 @@ class Core(Module, AutoCSR): coarse_ts = Signal(64-glbl_fine_ts_width) self.sync.rtio += coarse_ts.eq(coarse_ts + 1) - coarse_ts_cdc = GrayCodeTransfer(len(coarse_ts)) + coarse_ts_cdc = GrayCodeTransfer(len(coarse_ts)) # from rtio to sys self.submodules += coarse_ts_cdc self.comb += [ coarse_ts_cdc.i.eq(coarse_ts), @@ -83,7 +83,7 @@ class Core(Module, AutoCSR): interface=self.cri) self.submodules += outputs self.comb += outputs.coarse_timestamp.eq(coarse_ts) - self.sync += outputs.minimum_coarse_timestamp.eq(coarse_ts + 16) + self.sync += outputs.minimum_coarse_timestamp.eq(coarse_ts_cdc.o + 16) inputs = InputCollector(channels, glbl_fine_ts_width, "async", quash_channels=quash_channels,