From a61d701d47eb67b7f1515b35c7674091185f38b9 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 2 May 2015 11:47:11 +0800 Subject: [PATCH] rtio: decouple PHY reset from logic reset --- artiq/gateware/rtio/core.py | 7 ++++++- artiq/gateware/rtio/phy/ttl_simple.py | 8 ++++---- artiq/gateware/rtio/phy/wishbone.py | 2 +- soc/runtime/rtio.c | 1 + soc/targets/artiq_kc705.py | 2 +- soc/targets/artiq_pipistrello.py | 2 +- 6 files changed, 14 insertions(+), 8 deletions(-) diff --git a/artiq/gateware/rtio/core.py b/artiq/gateware/rtio/core.py index 96c382324..946ded34d 100644 --- a/artiq/gateware/rtio/core.py +++ b/artiq/gateware/rtio/core.py @@ -257,6 +257,7 @@ class _KernelCSRs(AutoCSR): def __init__(self, chan_sel_width, data_width, address_width, full_ts_width): self.reset = CSRStorage(reset=1) + self.reset_phy = CSRStorage(reset=1) self.chan_sel = CSRStorage(chan_sel_width) if data_width: @@ -296,10 +297,11 @@ class RTIO(Module): full_ts_width) # Clocking/Reset - # Create rsys and rio domains based on sys and rio + # Create rsys, rio and rio_phy domains based on sys and rtio # with reset controlled by CSR. self.clock_domains.cd_rsys = ClockDomain() self.clock_domains.cd_rio = ClockDomain() + self.clock_domains.cd_rio_phy = ClockDomain() self.comb += [ self.cd_rsys.clk.eq(ClockSignal()), self.cd_rsys.rst.eq(self.kcsrs.reset.storage) @@ -307,6 +309,9 @@ class RTIO(Module): self.comb += self.cd_rio.clk.eq(ClockSignal("rtio")) self.specials += AsyncResetSynchronizer(self.cd_rio, self.kcsrs.reset.storage) + self.comb += self.cd_rio_phy.clk.eq(ClockSignal("rtio")) + self.specials += AsyncResetSynchronizer(self.cd_rio_phy, + self.kcsrs.reset_phy.storage) # Managers self.submodules.counter = _RTIOCounter(full_ts_width - fine_ts_width) diff --git a/artiq/gateware/rtio/phy/ttl_simple.py b/artiq/gateware/rtio/phy/ttl_simple.py index d1985a012..8a27fcb9a 100644 --- a/artiq/gateware/rtio/phy/ttl_simple.py +++ b/artiq/gateware/rtio/phy/ttl_simple.py @@ -10,7 +10,7 @@ class Output(Module): # # # - self.sync.rio += If(self.rtlink.o.stb, pad.eq(self.rtlink.o.data)) + self.sync.rio_phy += If(self.rtlink.o.stb, pad.eq(self.rtlink.o.data)) class Inout(Module): @@ -25,7 +25,7 @@ class Inout(Module): self.specials += ts.get_tristate(pad) sensitivity = Signal(2) - self.sync.rio += If(self.rtlink.o.stb, + self.sync.rio_phy += If(self.rtlink.o.stb, Case(self.rtlink.o.address, { 0: ts.o.eq(self.rtlink.o.data[0]), 1: ts.oe.eq(self.rtlink.o.data[0]), @@ -35,8 +35,8 @@ class Inout(Module): i = Signal() i_d = Signal() - self.specials += MultiReg(ts.i, i, "rio") - self.sync.rio += i_d.eq(i) + self.specials += MultiReg(ts.i, i, "rio_phy") + self.sync.rio_phy += i_d.eq(i) self.comb += [ self.rtlink.i.stb.eq( (sensitivity[0] & ( i & ~i_d)) | diff --git a/artiq/gateware/rtio/phy/wishbone.py b/artiq/gateware/rtio/phy/wishbone.py index c4c822d3c..773dcb9bf 100644 --- a/artiq/gateware/rtio/phy/wishbone.py +++ b/artiq/gateware/rtio/phy/wishbone.py @@ -18,7 +18,7 @@ class RT2WB(Module): # # # active = Signal() - self.sync.rio += [ + self.sync.rio_phy += [ If(self.rtlink.o.stb, active.eq(1), wb.adr.eq(self.rtlink.o.address[:address_width]), diff --git a/soc/runtime/rtio.c b/soc/runtime/rtio.c index 9f156b5cf..e1a2e9610 100644 --- a/soc/runtime/rtio.c +++ b/soc/runtime/rtio.c @@ -16,6 +16,7 @@ void rtio_init(void) previous_fud_end_time = 0; rtio_reset_write(1); rtio_reset_write(0); + rtio_reset_phy_write(0); } static void write_and_process_status(long long int timestamp, int channel) diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py index 88d25d5e9..1c5cbafdf 100644 --- a/soc/targets/artiq_kc705.py +++ b/soc/targets/artiq_kc705.py @@ -17,7 +17,7 @@ from artiq.gateware.rtio.phy import ttl_simple class _RTIOCRG(Module, AutoCSR): def __init__(self, platform, rtio_internal_clk): self._clock_sel = CSRStorage() - self.clock_domains.cd_rtio = ClockDomain() + self.clock_domains.cd_rtio = ClockDomain(reset_less=True) rtio_external_clk = Signal() user_sma_clock = platform.request("user_sma_clock") diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py index 33f4ff21b..fac40e2f6 100644 --- a/soc/targets/artiq_pipistrello.py +++ b/soc/targets/artiq_pipistrello.py @@ -14,7 +14,7 @@ from artiq.gateware.rtio.phy import ttl_simple class _RTIOCRG(Module, AutoCSR): def __init__(self, platform): self._clock_sel = CSRStorage() - self.clock_domains.cd_rtio = ClockDomain() + self.clock_domains.cd_rtio = ClockDomain(reset_less=True) # 75MHz -> 125MHz rtio_internal_clk = Signal()