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Revert "sayma: set up Si5324 for RGMII clock rerouting"

This reverts commit 2b01aa22b6.
This commit is contained in:
Sebastien Bourdeauducq 2017-12-21 14:42:15 +08:00
parent 701308474f
commit a23251276d
2 changed files with 0 additions and 32 deletions

View File

@ -82,8 +82,6 @@ fn startup() {
#[cfg(has_ad9154)] #[cfg(has_ad9154)]
board::ad9154::init().expect("cannot initialize AD9154"); board::ad9154::init().expect("cannot initialize AD9154");
#[cfg(rgmii_clock_rerouted)]
setup_rgmii_si5324();
#[cfg(has_ethmac)] #[cfg(has_ethmac)]
startup_ethernet(); startup_ethernet();
#[cfg(not(has_ethmac))] #[cfg(not(has_ethmac))]
@ -93,27 +91,6 @@ fn startup() {
} }
} }
#[cfg(rgmii_clock_rerouted)]
fn setup_rgmii_si5324()
{
const SI5324_SETTINGS: board::si5324::FrequencySettings
= board::si5324::FrequencySettings {
n1_hs : 5,
nc1_ls : 8,
n2_hs : 7,
n2_ls : 360,
n31 : 63,
n32 : 63,
bwsel : 4
};
info!("rerouting RGMII clock through Si5324");
unsafe { board::csr::ethphy::crg_reset_write(1); }
board::i2c::init();
board::si5324::setup(&SI5324_SETTINGS).expect("cannot initialize Si5324");
board::si5324::select_ext_input(true).expect("failed to select Si5324 input");
unsafe { board::csr::ethphy::crg_reset_write(0); }
}
#[cfg(has_ethmac)] #[cfg(has_ethmac)]
fn startup_ethernet() { fn startup_ethernet() {
let hardware_addr; let hardware_addr;

View File

@ -140,15 +140,6 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
serial_rtm.tx.eq(serial_1.rx) serial_rtm.tx.eq(serial_1.rx)
] ]
# Si5324 used to work around RGMII clock routing issue on first PCB revision
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
# AMC/RTM serwb # AMC/RTM serwb
serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=2) serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=2)
self.comb += serwb_pll.refclk.eq(self.crg.cd_sys.clk) self.comb += serwb_pll.refclk.eq(self.crg.cd_sys.clk)