forked from M-Labs/artiq
docs: fix syntax
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@ -92,14 +92,15 @@ class Phaser:
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that have different features. Phaser mode and coredevice PHY are both
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that have different features. Phaser mode and coredevice PHY are both
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both selected at gateware compile-time and need to match.
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both selected at gateware compile-time and need to match.
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Phaser gateware | Coredevice PHY | Features per :class:`PhaserChannel`
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=============== ============== ===================================
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--------------- | -------------- | -----------------------------------
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Phaser gateware Coredevice PHY Features per :class:`PhaserChannel`
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Base <= v0.5 | Base | Base (5 :class:`PhaserOscillator`)
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=============== ============== ===================================
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Base >= v0.6 | Base | Base + Servo
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Base <= v0.5 Base Base (5 :class:`PhaserOscillator`)
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Miqro >= v0.6 | Miqro | :class:`Miqro`
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Base >= v0.6 Base Base + Servo
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Miqro >= v0.6 Miqro :class:`Miqro`
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=============== ============== ===================================
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Base mode
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**Base mode**
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---------
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The coredevice produces 2 IQ (in-phase and quadrature) data streams with 25
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The coredevice produces 2 IQ (in-phase and quadrature) data streams with 25
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MS/s and 14 bit per quadrature. Each data stream supports 5 independent
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MS/s and 14 bit per quadrature. Each data stream supports 5 independent
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@ -131,15 +132,13 @@ class Phaser:
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absolute phase with respect to other RTIO input and output events
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absolute phase with respect to other RTIO input and output events
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(see `get_next_frame_mu()`).
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(see `get_next_frame_mu()`).
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Miqro mode
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**Miqro mode**
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----------
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See :class:`Miqro`
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See :class:`Miqro`
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Here the DAC operates in 4x interpolation.
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Here the DAC operates in 4x interpolation.
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Analog flow
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**Analog flow**
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-----------
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The four analog DAC outputs are passed through anti-aliasing filters.
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The four analog DAC outputs are passed through anti-aliasing filters.
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@ -158,8 +157,7 @@ class Phaser:
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configured through a shared SPI bus that is accessed and controlled via
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configured through a shared SPI bus that is accessed and controlled via
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FPGA registers.
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FPGA registers.
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Servo
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**Servo**
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-----
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Each phaser output channel features a servo to control the RF output amplitude
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Each phaser output channel features a servo to control the RF output amplitude
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using feedback from an ADC. The servo consists of a first order IIR (infinite
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using feedback from an ADC. The servo consists of a first order IIR (infinite
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@ -1193,8 +1191,8 @@ class PhaserChannel:
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Gains are given in units of output full per scale per input full scale.
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Gains are given in units of output full per scale per input full scale.
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.. note:: Due to inherent constraints of the fixed point datatypes and IIR
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.. note:: Due to inherent constraints of the fixed point datatypes and IIR
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filters, the ``x_offset`` (setpoint) resolution depends on the selected gains.
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filters, the ``x_offset`` (setpoint) resolution depends on the selected
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Low ``ki`` gains will lead to a low ``x_offset`` resolution.
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gains. Low ``ki`` gains will lead to a low ``x_offset`` resolution.
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The transfer function is (up to time discretization and
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The transfer function is (up to time discretization and
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coefficient quantization errors):
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coefficient quantization errors):
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@ -1323,8 +1321,7 @@ class Miqro:
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contained in the Phaser gateware. The output is generated by with
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contained in the Phaser gateware. The output is generated by with
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the following data flow:
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the following data flow:
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Oscillators
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**Oscillators**
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...........
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* There are n_osc = 16 oscillators with oscillator IDs 0..n_osc-1.
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* There are n_osc = 16 oscillators with oscillator IDs 0..n_osc-1.
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* Each oscillator outputs one tone at any given time
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* Each oscillator outputs one tone at any given time
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@ -1359,16 +1356,14 @@ class Miqro:
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during fast pulse sequences. They are intended for use in calibration and
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during fast pulse sequences. They are intended for use in calibration and
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initialization.
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initialization.
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Summation
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**Summation**
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.........
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* The oscillator outputs are added together (wrapping addition).
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* The oscillator outputs are added together (wrapping addition).
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* The user must ensure that the sum of oscillators outputs does not exceed the
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* The user must ensure that the sum of oscillators outputs does not exceed the
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data range. In general that means that the sum of the amplitudes must not
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data range. In general that means that the sum of the amplitudes must not
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exceed one.
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exceed one.
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Shaper
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**Shaper**
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......
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* The summed complex output stream is then multiplied with a the complex-valued
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* The summed complex output stream is then multiplied with a the complex-valued
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output of a triggerable shaper.
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output of a triggerable shaper.
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@ -1393,8 +1388,7 @@ class Miqro:
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each window respectively. This is used to implement pulses with arbitrary
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each window respectively. This is used to implement pulses with arbitrary
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length or CW output.
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length or CW output.
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Overall properties
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**Overall properties**
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..................
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* The DAC may upconvert the signal by applying a frequency offset f1 with
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* The DAC may upconvert the signal by applying a frequency offset f1 with
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phase p1.
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phase p1.
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