diff --git a/artiq/coredevice/phaser.py b/artiq/coredevice/phaser.py
index 8a7131c2d..bc82c8751 100644
--- a/artiq/coredevice/phaser.py
+++ b/artiq/coredevice/phaser.py
@@ -92,14 +92,15 @@ class Phaser:
     that have different features. Phaser mode and coredevice PHY are both
     both selected at gateware compile-time and need to match.
 
-    Phaser gateware | Coredevice PHY | Features per :class:`PhaserChannel`
-    --------------- | -------------- | -----------------------------------
-    Base <= v0.5    | Base           | Base (5 :class:`PhaserOscillator`)
-    Base >= v0.6    | Base           | Base + Servo
-    Miqro >= v0.6   | Miqro          | :class:`Miqro`
+    ===============  ==============  ===================================
+    Phaser gateware  Coredevice PHY  Features per :class:`PhaserChannel`
+    ===============  ==============  ===================================
+    Base <= v0.5     Base            Base (5 :class:`PhaserOscillator`)
+    Base >= v0.6     Base            Base + Servo
+    Miqro >= v0.6    Miqro           :class:`Miqro`
+    ===============  ==============  ===================================
 
-    Base mode
-    ---------
+    **Base mode**
 
     The coredevice produces 2 IQ (in-phase and quadrature) data streams with 25
     MS/s and 14 bit per quadrature. Each data stream supports 5 independent
@@ -131,15 +132,13 @@ class Phaser:
     absolute phase with respect to other RTIO input and output events
     (see `get_next_frame_mu()`).
 
-    Miqro mode
-    ----------
+    **Miqro mode**
 
     See :class:`Miqro`
 
     Here the DAC operates in 4x interpolation.
 
-    Analog flow
-    -----------
+    **Analog flow**
 
     The four analog DAC outputs are passed through anti-aliasing filters.
 
@@ -158,8 +157,7 @@ class Phaser:
     configured through a shared SPI bus that is accessed and controlled via
     FPGA registers.
 
-    Servo
-    -----
+    **Servo**
 
     Each phaser output channel features a servo to control the RF output amplitude
     using feedback from an ADC. The servo consists of a first order IIR (infinite
@@ -1193,8 +1191,8 @@ class PhaserChannel:
         Gains are given in units of output full per scale per input full scale.
 
         .. note:: Due to inherent constraints of the fixed point datatypes and IIR
-        filters, the ``x_offset`` (setpoint) resolution depends on the selected gains. 
-        Low ``ki`` gains will lead to a low ``x_offset`` resolution.
+            filters, the ``x_offset`` (setpoint) resolution depends on the selected
+            gains. Low ``ki`` gains will lead to a low ``x_offset`` resolution.
 
         The transfer function is (up to time discretization and
         coefficient quantization errors):
@@ -1323,8 +1321,7 @@ class Miqro:
     contained in the Phaser gateware. The output is generated by with
     the following data flow:
 
-    Oscillators
-    ...........
+    **Oscillators**
 
     * There are n_osc = 16 oscillators with oscillator IDs 0..n_osc-1.
     * Each oscillator outputs one tone at any given time
@@ -1359,16 +1356,14 @@ class Miqro:
       during fast pulse sequences. They are intended for use in calibration and
       initialization.
 
-    Summation
-    .........
+    **Summation**
 
     * The oscillator outputs are added together (wrapping addition).
     * The user must ensure that the sum of oscillators outputs does not exceed the
       data range. In general that means that the sum of the amplitudes must not
       exceed one.
 
-    Shaper
-    ......
+    **Shaper**
 
     * The summed complex output stream is then multiplied with a the complex-valued
       output of a triggerable shaper.
@@ -1393,8 +1388,7 @@ class Miqro:
       each window respectively. This is used to implement pulses with arbitrary
       length or CW output.
 
-    Overall properties
-    ..................
+    **Overall properties**
 
     * The DAC may upconvert the signal by applying a frequency offset f1 with
       phase p1.