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kc705: cleanup

This commit is contained in:
Harry Ho 2021-01-21 11:30:11 +08:00
parent 7c4eed7a11
commit a0fd5261ea
4 changed files with 4 additions and 17 deletions
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7
artiq/gateware/drtio/transceiver/gtx_7series.py
View File

@ -228,13 +228,6 @@ class GTX_20X(Module):
p_RXCDR_PH_RESET_ON_EIDLE=0b0,
p_RXCDR_LOCK_CFG=0b010101,
# # RX Initialization and Reset Attributes
# p_RXCDRFREQRESET_TIME=0b00001,
# p_RXCDRPHRESET_TIME=0b00001,
# p_RXISCANRESET_TIME=0b00001,
# p_RXPCSRESET_TIME=0b00001,
# p_RXPMARESET_TIME=0b00011,
# Pads
i_GTXRXP=rx_pads.p,
i_GTXRXN=rx_pads.n,

8
artiq/gateware/drtio/transceiver/gtx_7series_init.py
View File

@ -1,9 +1,7 @@
from math import ceil
from functools import reduce
from operator import add
from migen import *
from migen.genlib.cdc import MultiReg, PulseSynchronizer
from migen.genlib.cdc import MultiReg
from migen.genlib.misc import WaitTimer
from migen.genlib.fsm import FSM
@ -137,7 +135,7 @@ class GTXInit(Module):
If(Xxresetdone, NextState("DELAY_ALIGN"))
)
# State(s) exclusive to Auto Mode:
# States exclusive to Auto Mode:
if mode == "single":
# Start delay alignment (pulse)
startup_fsm.act("DELAY_ALIGN",
@ -161,7 +159,7 @@ class GTXInit(Module):
If(Xxphaligndone_rising, NextState("READY"))
)
# State(s) exclusive to Manual Mode:
# States exclusive to Manual Mode:
else:
# Start delay alignment (hold)
startup_fsm.act("DELAY_ALIGN",

2
artiq/gateware/targets/kc705_drtio_master.py
View File

@ -9,8 +9,8 @@ from migen.build.xilinx.ise import XilinxISEToolchain
from misoc.cores import spi as spi_csr
from misoc.cores import gpio
from misoc.integration.builder import *
from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
from misoc.integration.builder import builder_args, builder_argdict
from artiq.gateware.amp import AMPSoC
from artiq.gateware import rtio

4
artiq/gateware/targets/kc705_drtio_satellite.py
View File

@ -1,7 +1,6 @@
#!/usr/bin/env python3
import argparse
import os
from migen import *
from migen.build.generic_platform import *
@ -21,9 +20,6 @@ from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
from artiq.gateware.drtio import *
from artiq.build_soc import *
# DEBUG
from microscope import *
class Satellite(BaseSoC):
mem_map = {