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ad9910: add init bit explanation 

Signed-off-by: Robert Jördens <rj@quartiq.de>
This commit is contained in:
Robert Jördens 2018-11-05 12:52:33 +00:00
parent bc04da15c5
commit 9fb850ae75
1 changed files with 3 additions and 0 deletions
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3
artiq/coredevice/ad9910.py
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@ -215,6 +215,9 @@ class AD9910:
raise ValueError("Urukul AD9910 AUX_DAC mismatch") raise ValueError("Urukul AD9910 AUX_DAC mismatch")
delay(50*us) # slack delay(50*us) # slack
# Configure PLL settings and bring up PLL # Configure PLL settings and bring up PLL
# enable amplitude scale from profiles
# read effective FTW
# sync timing validation disable (enabled later)
self.write32(_AD9910_REG_CFR2, 0x01010020) self.write32(_AD9910_REG_CFR2, 0x01010020)
self.cpld.io_update.pulse(1*us) self.cpld.io_update.pulse(1*us)
cfr3 = (0x0807c100 | (self.pll_vco << 24) | cfr3 = (0x0807c100 | (self.pll_vco << 24) |