diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py
index 9794b6c5b..740b68b22 100644
--- a/soc/targets/artiq_kc705.py
+++ b/soc/targets/artiq_kc705.py
@@ -83,7 +83,9 @@ class NIST_QC1(MiniSoC, AMPSoC):
         self.add_constant("DDS_CHANNEL_COUNT", 8)
         phy = dds.AD9858(platform.request("dds"))
         self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
+        rtio_channels.append(rtio.Channel.from_phy(phy,
+                                                   ofifo_depth=512,
+                                                   ififo_depth=4))
 
         # RTIO core
         self.submodules.rtio_crg = _RTIOCRG(platform, self.crg.pll_sys)
diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py
index 17ca3f6c6..96c595f5b 100644
--- a/soc/targets/artiq_pipistrello.py
+++ b/soc/targets/artiq_pipistrello.py
@@ -118,7 +118,9 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
         self.add_constant("DDS_CHANNEL_COUNT", 8)
         phy = dds.AD9858(platform.request("dds"))
         self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
+        rtio_channels.append(rtio.Channel.from_phy(phy,
+                                                   ofifo_depth=512,
+                                                   ififo_depth=4))
 
         # RTIO core
         self.submodules.rtio_crg = _RTIOCRG(platform)