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kasli: fix SYSU TTL directions

This commit is contained in:
Sebastien Bourdeauducq 2018-08-07 19:28:40 +08:00
parent 8aa88cfe70
commit 9ce6233926
2 changed files with 5 additions and 3 deletions
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2
artiq/examples/kasli_basic/device_db_sysu.py
View File

@ -42,7 +42,7 @@ for i in range(40):
device_db["ttl" + str(i)] = { device_db["ttl" + str(i)] = {
"type": "local", "type": "local",
"module": "artiq.coredevice.ttl", "module": "artiq.coredevice.ttl",
"class": "TTLInOut" if i < 4 else "TTLOut", "class": "TTLInOut" if i < 16 else "TTLOut",
"arguments": {"channel": i}, "arguments": {"channel": i},
} }

6
artiq/gateware/targets/kasli.py
View File

@ -246,8 +246,10 @@ class SYSU(_StandaloneBase):
self.rtio_channels = [] self.rtio_channels = []
eem.DIO.add_std(self, 2, eem.DIO.add_std(self, 2,
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X) ttl_serdes_7series.InOut_8X, ttl_serdes_7series.InOut_8X)
for i in range(3, 7): eem.DIO.add_std(self, 3,
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.InOut_8X)
for i in range(4, 7):
eem.DIO.add_std(self, i, eem.DIO.add_std(self, i,
ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X) ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
eem.Urukul.add_std(self, 1, 0, ttl_serdes_7series.Output_8X) eem.Urukul.add_std(self, 1, 0, ttl_serdes_7series.Output_8X)