forked from M-Labs/artiq
gateware/test/serwb: use unittest for in test_etherbone
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@ -1,3 +1,6 @@
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import unittest
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import random
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from migen import *
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from misoc.interconnect.wishbone import SRAM
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@ -25,7 +28,7 @@ class DUT(Module):
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master_packetizer = packet.Packetizer()
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self.submodules += master_depacketizer, master_packetizer
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master_etherbone = etherbone.Etherbone(mode="master")
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master_sram = SRAM(1024, bus=master_etherbone.wishbone.bus)
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master_sram = SRAM(64, bus=master_etherbone.wishbone.bus)
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self.submodules += master_etherbone, master_sram
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self.comb += [
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master_depacketizer.source.connect(master_etherbone.sink),
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@ -53,14 +56,15 @@ class DUT(Module):
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self.wishbone = slave_etherbone.wishbone.bus
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def main_generator(dut):
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for i in range(8):
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yield from dut.wishbone.write(0x100 + i, i)
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for i in range(8):
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data = (yield from dut.wishbone.read(0x100 + i))
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print("0x{:08x}".format(data))
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if __name__ == "__main__":
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dut = DUT()
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run_simulation(dut, main_generator(dut), vcd_name="sim.vcd")
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class TestEtherbone(unittest.TestCase):
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def test_write_read_sram(self):
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dut = DUT()
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prng = random.Random(1)
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def generator(dut):
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datas = [prng.randrange(0, 2**32-1) for i in range(16)]
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for i in range(16):
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yield from dut.wishbone.write(i, datas[i])
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for i in range(16):
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data = (yield from dut.wishbone.read(i))
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self.assertEqual(data, datas[i])
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run_simulation(dut, generator(dut))
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