forked from M-Labs/artiq
gateware/serwb: generate wishbone error if link loose ready in the middle of a transaction
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@ -667,33 +667,43 @@ class EtherboneWishboneSlave(Module):
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)
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)
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fsm.act("SEND_WRITE",
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source.stb.eq(1),
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source.eop.eq(1),
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source.base_addr[2:].eq(bus.adr),
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source.count.eq(1),
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source.be.eq(bus.sel),
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source.we.eq(1),
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source.data.eq(bus.dat_w),
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If(source.stb & source.ack,
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bus.ack.eq(1),
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NextState("IDLE")
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If(~self.ready,
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NextState("SEND_ERROR")
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).Else(
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source.stb.eq(1),
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source.eop.eq(1),
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source.base_addr[2:].eq(bus.adr),
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source.count.eq(1),
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source.be.eq(bus.sel),
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source.we.eq(1),
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source.data.eq(bus.dat_w),
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If(source.stb & source.ack,
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bus.ack.eq(1),
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NextState("IDLE")
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)
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)
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)
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fsm.act("SEND_READ",
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source.stb.eq(1),
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source.eop.eq(1),
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source.base_addr.eq(0),
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source.count.eq(1),
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source.be.eq(bus.sel),
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source.we.eq(0),
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source.data[2:].eq(bus.adr),
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If(source.stb & source.ack,
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NextState("WAIT_READ")
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If(~self.ready,
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NextState("SEND_ERROR")
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).Else(
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source.stb.eq(1),
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source.eop.eq(1),
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source.base_addr.eq(0),
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source.count.eq(1),
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source.be.eq(bus.sel),
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source.we.eq(0),
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source.data[2:].eq(bus.adr),
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If(source.stb & source.ack,
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NextState("WAIT_READ")
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)
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)
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)
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fsm.act("WAIT_READ",
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sink.ack.eq(1),
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If(sink.stb & sink.we,
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If(~self.ready,
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NextState("SEND_ERROR")
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).Elif(sink.stb & sink.we,
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bus.ack.eq(1),
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bus.dat_r.eq(sink.data),
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NextState("IDLE")
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