forked from M-Labs/artiq
adapt to migen/misoc changes
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parent
da5208e160
commit
9aa94e1a2d
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@ -3,7 +3,7 @@ from operator import xor, or_
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from migen import *
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from migen import *
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from migen.genlib.fsm import *
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from migen.genlib.fsm import *
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from migen.genlib.cdc import MultiReg, NoRetiming
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from migen.genlib.cdc import MultiReg
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class Scrambler(Module):
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class Scrambler(Module):
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@ -240,10 +240,8 @@ class LinkLayer(Module):
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ready_r = Signal()
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ready_r = Signal()
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ready_rx = Signal()
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ready_rx = Signal()
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self.sync.rtio += ready_r.eq(self.ready)
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self.sync.rtio += ready_r.eq(self.ready)
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self.specials += [
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ready_r.attr.add("no_retiming")
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NoRetiming(ready_r),
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self.specials += MultiReg(ready_r, ready_rx, "rtio_rx")
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MultiReg(ready_r, ready_rx, "rtio_rx")
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]
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self.comb += [
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self.comb += [
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self.rx_aux_frame.eq(rx.aux_frame & ready_rx),
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self.rx_aux_frame.eq(rx.aux_frame & ready_rx),
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self.rx_rt_frame.eq(rx.rt_frame & ready_rx),
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self.rx_rt_frame.eq(rx.rt_frame & ready_rx),
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@ -259,10 +257,10 @@ class LinkLayer(Module):
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rx_remote_rx_ready = Signal()
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rx_remote_rx_ready = Signal()
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rx_link_init = Signal()
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rx_link_init = Signal()
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rx.remote_rx_ready.attr.add("no_retiming")
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rx.link_init.attr.add("no_retiming")
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self.specials += [
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self.specials += [
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NoRetiming(rx.remote_rx_ready),
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MultiReg(rx.remote_rx_ready, rx_remote_rx_ready, "rtio"),
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MultiReg(rx.remote_rx_ready, rx_remote_rx_ready, "rtio"),
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NoRetiming(rx.link_init),
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MultiReg(rx.link_init, rx_link_init, "rtio")
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MultiReg(rx.link_init, rx_link_init, "rtio")
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]
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]
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@ -1,5 +1,5 @@
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from migen import *
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from migen import *
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from migen.genlib.cdc import MultiReg, NoRetiming
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from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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from misoc.interconnect.csr import *
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@ -44,10 +44,8 @@ class RTController(Module):
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self.sync += If(self.kcsrs.counter_update.re,
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self.sync += If(self.kcsrs.counter_update.re,
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self.kcsrs.counter.status.eq(self.counter.value_sys))
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self.kcsrs.counter.status.eq(self.counter.value_sys))
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tsc_correction = Signal(64)
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tsc_correction = Signal(64)
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self.specials += [
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self.kcsrs.tsc_correction.storage.attr.add("no_retiming")
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NoRetiming(self.kcsrs.tsc_correction.storage),
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self.specials += MultiReg(self.kcsrs.tsc_correction.storage, tsc_correction)
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MultiReg(self.kcsrs.tsc_correction.storage, tsc_correction)
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]
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self.comb += [
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self.comb += [
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rt_packets.tsc_value.eq(
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rt_packets.tsc_value.eq(
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self.counter.value_rtio + tsc_correction),
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self.counter.value_rtio + tsc_correction),
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@ -3,7 +3,7 @@ from types import SimpleNamespace
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from migen import *
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from migen import *
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from migen.genlib.fsm import *
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from migen.genlib.fsm import *
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.cdc import PulseSynchronizer, NoRetiming
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from migen.genlib.cdc import PulseSynchronizer
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def layout_len(l):
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def layout_len(l):
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@ -334,7 +334,7 @@ class _CrossDomainRequest(Module):
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]
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]
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if req_data is not None:
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if req_data is not None:
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req_data_r = Signal.like(req_data)
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req_data_r = Signal.like(req_data)
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self.specials += NoRetiming(req_data_r)
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req_data_r.attr.add("no_retiming")
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self.sync += If(req_stb, req_data_r.eq(req_data))
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self.sync += If(req_stb, req_data_r.eq(req_data))
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dsync += [
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dsync += [
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If(request.o, srv_stb.eq(1)),
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If(request.o, srv_stb.eq(1)),
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@ -350,7 +350,7 @@ class _CrossDomainNotification(Module):
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emi_stb, emi_data,
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emi_stb, emi_data,
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rec_stb, rec_ack, rec_data):
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rec_stb, rec_ack, rec_data):
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emi_data_r = Signal.like(emi_data)
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emi_data_r = Signal.like(emi_data)
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self.specials += NoRetiming(emi_data_r)
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emi_data_r.attr.add("no_retiming")
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dsync = getattr(self.sync, domain)
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dsync = getattr(self.sync, domain)
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dsync += If(emi_stb, emi_data_r.eq(emi_data))
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dsync += If(emi_stb, emi_data_r.eq(emi_data))
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@ -18,10 +18,8 @@ class GrayCodeTransfer(Module):
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self.sync.rtio += value_gray_rtio.eq(self.i ^ self.i[1:])
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self.sync.rtio += value_gray_rtio.eq(self.i ^ self.i[1:])
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# transfer to system clock domain
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# transfer to system clock domain
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value_gray_sys = Signal(width)
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value_gray_sys = Signal(width)
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self.specials += [
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value_gray_rtio.attr.add("no_retiming")
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NoRetiming(value_gray_rtio),
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self.specials += MultiReg(value_gray_rtio, value_gray_sys)
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MultiReg(value_gray_rtio, value_gray_sys)
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]
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# convert back to binary
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# convert back to binary
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value_sys = Signal(width)
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value_sys = Signal(width)
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self.comb += value_sys[-1].eq(value_gray_sys[-1])
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self.comb += value_sys[-1].eq(value_gray_sys[-1])
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@ -8,7 +8,6 @@ from migen.genlib.cdc import MultiReg
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from migen.build.generic_platform import *
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from migen.build.generic_platform import *
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from migen.build.xilinx.vivado import XilinxVivadoToolchain
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from migen.build.xilinx.vivado import XilinxVivadoToolchain
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from migen.build.xilinx.ise import XilinxISEToolchain
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from migen.build.xilinx.ise import XilinxISEToolchain
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from migen.fhdl.specials import Keep
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from misoc.interconnect.csr import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import wishbone
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from misoc.interconnect import wishbone
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@ -147,22 +146,11 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.csr_devices.append("rtio_moninj")
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self.specials += [
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self.rtio_crg.cd_rtio.clk.attr.add("keep")
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Keep(self.rtio.cd_rsys.clk),
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Keep(self.rtio_crg.cd_rtio.clk),
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Keep(self.ethphy.crg.cd_eth_rx.clk),
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Keep(self.ethphy.crg.cd_eth_tx.clk),
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]
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self.platform.add_period_constraint(self.rtio.cd_rsys.clk, 8.)
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.)
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self.platform.add_false_path_constraints(
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self.platform.add_false_path_constraints(
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self.rtio.cd_rsys.clk,
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self.crg.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk,
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self.rtio_crg.cd_rtio.clk)
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self.ethphy.crg.cd_eth_rx.clk,
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self.ethphy.crg.cd_eth_tx.clk)
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
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self.get_native_sdram_if())
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self.get_native_sdram_if())
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@ -3,7 +3,6 @@
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import argparse
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import argparse
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from migen import *
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from migen import *
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from migen.fhdl.specials import Keep
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from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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@ -44,17 +43,6 @@ class Master(MiniSoC, AMPSoC):
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self.submodules.drtio = DRTIOMaster(self.transceiver)
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self.submodules.drtio = DRTIOMaster(self.transceiver)
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self.register_kernel_cpu_csrdevice("drtio")
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self.register_kernel_cpu_csrdevice("drtio")
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self.specials += [
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Keep(self.ethphy.crg.cd_eth_rx.clk),
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Keep(self.ethphy.crg.cd_eth_tx.clk),
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]
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platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.)
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platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.)
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platform.add_false_path_constraints(
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self.ethphy.crg.cd_eth_rx.clk,
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self.ethphy.crg.cd_eth_tx.clk)
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def main():
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def main():
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parser = argparse.ArgumentParser(
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parser = argparse.ArgumentParser(
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