From 9aa94e1a2d6cda70be080cd5df90d0e6e745f07b Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 31 Oct 2016 00:53:01 +0800 Subject: [PATCH] adapt to migen/misoc changes --- artiq/gateware/drtio/link_layer.py | 12 +++++------- artiq/gateware/drtio/rt_controller.py | 8 +++----- artiq/gateware/drtio/rt_packets.py | 6 +++--- artiq/gateware/rtio/cdc.py | 6 ++---- artiq/gateware/targets/kc705.py | 18 +++--------------- artiq/gateware/targets/kc705_drtio_master.py | 12 ------------ 6 files changed, 16 insertions(+), 46 deletions(-) diff --git a/artiq/gateware/drtio/link_layer.py b/artiq/gateware/drtio/link_layer.py index a1946e228..82019092a 100644 --- a/artiq/gateware/drtio/link_layer.py +++ b/artiq/gateware/drtio/link_layer.py @@ -3,7 +3,7 @@ from operator import xor, or_ from migen import * from migen.genlib.fsm import * -from migen.genlib.cdc import MultiReg, NoRetiming +from migen.genlib.cdc import MultiReg class Scrambler(Module): @@ -240,10 +240,8 @@ class LinkLayer(Module): ready_r = Signal() ready_rx = Signal() self.sync.rtio += ready_r.eq(self.ready) - self.specials += [ - NoRetiming(ready_r), - MultiReg(ready_r, ready_rx, "rtio_rx") - ] + ready_r.attr.add("no_retiming") + self.specials += MultiReg(ready_r, ready_rx, "rtio_rx") self.comb += [ self.rx_aux_frame.eq(rx.aux_frame & ready_rx), self.rx_rt_frame.eq(rx.rt_frame & ready_rx), @@ -259,10 +257,10 @@ class LinkLayer(Module): rx_remote_rx_ready = Signal() rx_link_init = Signal() + rx.remote_rx_ready.attr.add("no_retiming") + rx.link_init.attr.add("no_retiming") self.specials += [ - NoRetiming(rx.remote_rx_ready), MultiReg(rx.remote_rx_ready, rx_remote_rx_ready, "rtio"), - NoRetiming(rx.link_init), MultiReg(rx.link_init, rx_link_init, "rtio") ] diff --git a/artiq/gateware/drtio/rt_controller.py b/artiq/gateware/drtio/rt_controller.py index acee322ee..753b04f7b 100644 --- a/artiq/gateware/drtio/rt_controller.py +++ b/artiq/gateware/drtio/rt_controller.py @@ -1,5 +1,5 @@ from migen import * -from migen.genlib.cdc import MultiReg, NoRetiming +from migen.genlib.cdc import MultiReg from misoc.interconnect.csr import * @@ -44,10 +44,8 @@ class RTController(Module): self.sync += If(self.kcsrs.counter_update.re, self.kcsrs.counter.status.eq(self.counter.value_sys)) tsc_correction = Signal(64) - self.specials += [ - NoRetiming(self.kcsrs.tsc_correction.storage), - MultiReg(self.kcsrs.tsc_correction.storage, tsc_correction) - ] + self.kcsrs.tsc_correction.storage.attr.add("no_retiming") + self.specials += MultiReg(self.kcsrs.tsc_correction.storage, tsc_correction) self.comb += [ rt_packets.tsc_value.eq( self.counter.value_rtio + tsc_correction), diff --git a/artiq/gateware/drtio/rt_packets.py b/artiq/gateware/drtio/rt_packets.py index 3a3818f48..f756fb70a 100644 --- a/artiq/gateware/drtio/rt_packets.py +++ b/artiq/gateware/drtio/rt_packets.py @@ -3,7 +3,7 @@ from types import SimpleNamespace from migen import * from migen.genlib.fsm import * from migen.genlib.fifo import AsyncFIFO -from migen.genlib.cdc import PulseSynchronizer, NoRetiming +from migen.genlib.cdc import PulseSynchronizer def layout_len(l): @@ -334,7 +334,7 @@ class _CrossDomainRequest(Module): ] if req_data is not None: req_data_r = Signal.like(req_data) - self.specials += NoRetiming(req_data_r) + req_data_r.attr.add("no_retiming") self.sync += If(req_stb, req_data_r.eq(req_data)) dsync += [ If(request.o, srv_stb.eq(1)), @@ -350,7 +350,7 @@ class _CrossDomainNotification(Module): emi_stb, emi_data, rec_stb, rec_ack, rec_data): emi_data_r = Signal.like(emi_data) - self.specials += NoRetiming(emi_data_r) + emi_data_r.attr.add("no_retiming") dsync = getattr(self.sync, domain) dsync += If(emi_stb, emi_data_r.eq(emi_data)) diff --git a/artiq/gateware/rtio/cdc.py b/artiq/gateware/rtio/cdc.py index 7b31eedcd..bc561ebbf 100644 --- a/artiq/gateware/rtio/cdc.py +++ b/artiq/gateware/rtio/cdc.py @@ -18,10 +18,8 @@ class GrayCodeTransfer(Module): self.sync.rtio += value_gray_rtio.eq(self.i ^ self.i[1:]) # transfer to system clock domain value_gray_sys = Signal(width) - self.specials += [ - NoRetiming(value_gray_rtio), - MultiReg(value_gray_rtio, value_gray_sys) - ] + value_gray_rtio.attr.add("no_retiming") + self.specials += MultiReg(value_gray_rtio, value_gray_sys) # convert back to binary value_sys = Signal(width) self.comb += value_sys[-1].eq(value_gray_sys[-1]) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 7209a2b3b..ea38273d4 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -8,7 +8,6 @@ from migen.genlib.cdc import MultiReg from migen.build.generic_platform import * from migen.build.xilinx.vivado import XilinxVivadoToolchain from migen.build.xilinx.ise import XilinxISEToolchain -from migen.fhdl.specials import Keep from misoc.interconnect.csr import * from misoc.interconnect import wishbone @@ -147,22 +146,11 @@ class _NIST_Ions(MiniSoC, AMPSoC): self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") - self.specials += [ - Keep(self.rtio.cd_rsys.clk), - Keep(self.rtio_crg.cd_rtio.clk), - Keep(self.ethphy.crg.cd_eth_rx.clk), - Keep(self.ethphy.crg.cd_eth_tx.clk), - ] - - self.platform.add_period_constraint(self.rtio.cd_rsys.clk, 8.) + self.rtio_crg.cd_rtio.clk.attr.add("keep") self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.) self.platform.add_false_path_constraints( - self.rtio.cd_rsys.clk, - self.rtio_crg.cd_rtio.clk, - self.ethphy.crg.cd_eth_rx.clk, - self.ethphy.crg.cd_eth_tx.clk) + self.crg.cd_sys.clk, + self.rtio_crg.cd_rtio.clk) self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio, self.get_native_sdram_if()) diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py index ecbf7b7ff..93118d70e 100755 --- a/artiq/gateware/targets/kc705_drtio_master.py +++ b/artiq/gateware/targets/kc705_drtio_master.py @@ -3,7 +3,6 @@ import argparse from migen import * -from migen.fhdl.specials import Keep from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict from misoc.integration.builder import builder_args, builder_argdict @@ -44,17 +43,6 @@ class Master(MiniSoC, AMPSoC): self.submodules.drtio = DRTIOMaster(self.transceiver) self.register_kernel_cpu_csrdevice("drtio") - self.specials += [ - Keep(self.ethphy.crg.cd_eth_rx.clk), - Keep(self.ethphy.crg.cd_eth_tx.clk), - ] - - platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.) - platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.) - platform.add_false_path_constraints( - self.ethphy.crg.cd_eth_rx.clk, - self.ethphy.crg.cd_eth_tx.clk) - def main(): parser = argparse.ArgumentParser(