forked from M-Labs/artiq
gateware.spi: simpler clk bias
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d5893d15fb
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9a881aa430
@ -20,7 +20,7 @@ class SPIClockGen(Module):
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cnt.eq(cnt - 1),
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If(self.edge,
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cnt.eq(self.load[1:] +
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(self.load[0] & self.bias)),
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(self.load[0] & (self.clk ^ self.bias))),
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self.clk.eq(~self.clk),
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)
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]
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@ -143,7 +143,7 @@ class SPIMachine(Module):
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).Else(
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self.cg.load.eq(self.div_read),
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),
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self.cg.bias.eq(fsm.before_entering("SETUP")),
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self.cg.bias.eq(self.clk_phase),
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fsm.ce.eq(self.cg.edge),
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self.cs.eq(~fsm.ongoing("IDLE")),
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self.reg.ce.eq(self.cg.edge),
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