From 9a881aa430c18b141ceb9ee804f765d953465be0 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Mon, 29 Feb 2016 00:36:18 +0100 Subject: [PATCH] gateware.spi: simpler clk bias --- artiq/gateware/spi.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/spi.py b/artiq/gateware/spi.py index 86ae26562..ebfa9a8b0 100644 --- a/artiq/gateware/spi.py +++ b/artiq/gateware/spi.py @@ -20,7 +20,7 @@ class SPIClockGen(Module): cnt.eq(cnt - 1), If(self.edge, cnt.eq(self.load[1:] + - (self.load[0] & self.bias)), + (self.load[0] & (self.clk ^ self.bias))), self.clk.eq(~self.clk), ) ] @@ -143,7 +143,7 @@ class SPIMachine(Module): ).Else( self.cg.load.eq(self.div_read), ), - self.cg.bias.eq(fsm.before_entering("SETUP")), + self.cg.bias.eq(self.clk_phase), fsm.ce.eq(self.cg.edge), self.cs.eq(~fsm.ongoing("IDLE")), self.reg.ce.eq(self.cg.edge),