srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

spi: fix xfers with full data_width (closes #615) 

misoc 15000af43611bbe8be13cb2b016e408f043202cd
This commit is contained in:
Robert Jördens 2017-01-03 19:50:15 +01:00
parent 6b7e6a53f7
commit 9a80b8d533
1 changed files with 8 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
artiq/gateware/spi.py
View File

@ -138,7 +138,7 @@ class SPIMaster(Module):
assert len(xfer) <= len(bus.dat_w)
self.submodules.spi = spi = SPIMachine(
data_width=len(bus.dat_w),
data_width=len(bus.dat_w) + 1,
clock_width=len(config.div_read),
bits_width=len(xfer.read_length))
@ -156,13 +156,18 @@ class SPIMaster(Module):
]
self.sync += [
If(spi.done,
data_read.eq(spi.reg.data),
data_read.eq(
Mux(spi.reg.lsb, spi.reg.data[1:], spi.reg.data[:-1])),
),
If(spi.start,
cs.eq(xfer.cs),
spi.bits.n_write.eq(xfer.write_length),
spi.bits.n_read.eq(xfer.read_length),
spi.reg.data.eq(data_write),
If(spi.reg.lsb,
spi.reg.data[:-1].eq(data_write),
).Else(
spi.reg.data[1:].eq(data_write),
),
pending.eq(0),
),
# wb.ack a transaction if any of the following: