From 9a80b8d5331c4703c0d5ea889d46b4b70fee1f72 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 3 Jan 2017 19:50:15 +0100 Subject: [PATCH] spi: fix xfers with full data_width (closes #615) misoc 15000af43611bbe8be13cb2b016e408f043202cd --- artiq/gateware/spi.py | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/spi.py b/artiq/gateware/spi.py index 23e52915f..2daa3907c 100644 --- a/artiq/gateware/spi.py +++ b/artiq/gateware/spi.py @@ -138,7 +138,7 @@ class SPIMaster(Module): assert len(xfer) <= len(bus.dat_w) self.submodules.spi = spi = SPIMachine( - data_width=len(bus.dat_w), + data_width=len(bus.dat_w) + 1, clock_width=len(config.div_read), bits_width=len(xfer.read_length)) @@ -156,13 +156,18 @@ class SPIMaster(Module): ] self.sync += [ If(spi.done, - data_read.eq(spi.reg.data), + data_read.eq( + Mux(spi.reg.lsb, spi.reg.data[1:], spi.reg.data[:-1])), ), If(spi.start, cs.eq(xfer.cs), spi.bits.n_write.eq(xfer.write_length), spi.bits.n_read.eq(xfer.read_length), - spi.reg.data.eq(data_write), + If(spi.reg.lsb, + spi.reg.data[:-1].eq(data_write), + ).Else( + spi.reg.data[1:].eq(data_write), + ), pending.eq(0), ), # wb.ack a transaction if any of the following: