forked from M-Labs/artiq
kasli: construct DRTIO-EEM modules before adding RTIO
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@ -99,10 +99,12 @@ class GenericMaster(MasterBase):
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"])
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if has_drtio_over_eem:
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self.add_eem_drtio(self.eem_drtio_channels)
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self.add_drtio_cpuif_groups()
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self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"])
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if has_grabber:
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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