forked from M-Labs/artiq
drtio: allow specifying 7series RXSynchronizer initial phase
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@ -208,7 +208,7 @@ class RXSynchronizer(Module, AutoCSR):
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Xilinx scriptures (when existent) and should be constant for a given design
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placement.
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"""
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def __init__(self, rtio_clk_freq):
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def __init__(self, rtio_clk_freq, initial_phase=0.0):
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self.phase_shift = CSR()
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self.phase_shift_done = CSRStatus()
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@ -228,6 +228,7 @@ class RXSynchronizer(Module, AutoCSR):
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p_CLKFBOUT_MULT_F=mmcm_mult,
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p_CLKOUT0_DIVIDE_F=mmcm_mult,
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p_CLKOUT0_PHASE=intial_phase,
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p_DIVCLK_DIVIDE=1,
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# According to Xilinx, there is no guarantee of input/output
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