forked from M-Labs/artiq
drtio: fix master TSC KCSR readout
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@ -38,7 +38,7 @@ class RTController(Module):
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# master RTIO counter and counter synchronization
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self.submodules.counter = RTIOCounter(64-fine_ts_width)
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self.sync += If(self.kcsrs.counter_update.re,
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self.kcsrs.counter.status.eq(self.counter.value_sys))
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self.kcsrs.counter.status.eq(self.counter.value_sys << fine_ts_width))
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tsc_correction = Signal(64)
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self.csrs.tsc_correction.storage.attr.add("no_retiming")
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self.specials += MultiReg(self.csrs.tsc_correction.storage, tsc_correction)
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