forked from M-Labs/artiq
drtio: allow specifying 7series RXSynchronizer initial phase
This commit is contained in:
parent
bcb5053fb6
commit
95acc9b9d4
|
@ -208,7 +208,7 @@ class RXSynchronizer(Module, AutoCSR):
|
||||||
Xilinx scriptures (when existent) and should be constant for a given design
|
Xilinx scriptures (when existent) and should be constant for a given design
|
||||||
placement.
|
placement.
|
||||||
"""
|
"""
|
||||||
def __init__(self, rtio_clk_freq):
|
def __init__(self, rtio_clk_freq, initial_phase=0.0):
|
||||||
self.phase_shift = CSR()
|
self.phase_shift = CSR()
|
||||||
self.phase_shift_done = CSRStatus()
|
self.phase_shift_done = CSRStatus()
|
||||||
|
|
||||||
|
@ -228,6 +228,7 @@ class RXSynchronizer(Module, AutoCSR):
|
||||||
|
|
||||||
p_CLKFBOUT_MULT_F=mmcm_mult,
|
p_CLKFBOUT_MULT_F=mmcm_mult,
|
||||||
p_CLKOUT0_DIVIDE_F=mmcm_mult,
|
p_CLKOUT0_DIVIDE_F=mmcm_mult,
|
||||||
|
p_CLKOUT0_PHASE=intial_phase,
|
||||||
p_DIVCLK_DIVIDE=1,
|
p_DIVCLK_DIVIDE=1,
|
||||||
|
|
||||||
# According to Xilinx, there is no guarantee of input/output
|
# According to Xilinx, there is no guarantee of input/output
|
||||||
|
|
Loading…
Reference in New Issue