forked from M-Labs/artiq
rtio: resetless -> reset_less
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117b361a06
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@ -331,12 +331,12 @@ class RTIO(Module):
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self.specials += AsyncResetSynchronizer(
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self.cd_rio,
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self.kcsrs.reset.storage | ResetSignal("rtio",
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allow_resetless=True))
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allow_reset_less=True))
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self.comb += self.cd_rio_phy.clk.eq(ClockSignal("rtio"))
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self.specials += AsyncResetSynchronizer(
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self.cd_rio_phy,
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self.kcsrs.reset_phy.storage | ResetSignal("rtio",
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allow_resetless=True))
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allow_reset_less=True))
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# Managers
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self.submodules.counter = _RTIOCounter(full_ts_width - fine_ts_width)
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