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examples: add DRTIO sines

This commit is contained in:
Sebastien Bourdeauducq 2018-06-20 22:39:40 +08:00
parent 28fb0fd754
commit 9288301543
1 changed files with 27 additions and 0 deletions

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from artiq.experiment import *
class SAWGTestDRTIO(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("ttl_sma_out")
self.sawgs = [self.get_device("sawg"+str(8+i)) for i in range(8)]
@kernel
def run(self):
core_log("waiting for DRTIO ready...")
while not self.core.get_drtio_link_status(0):
pass
core_log("OK")
self.core.reset()
for sawg in self.sawgs:
delay(1*ms)
sawg.amplitude1.set(.4)
# Do not use a sub-multiple of oscilloscope sample rates.
sawg.frequency0.set(9*MHz)
while True:
delay(0.5*ms)
self.ttl_sma_out.pulse(0.5*ms)