From 9288301543183a262039c492e9e9b46ba89f1c91 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 20 Jun 2018 22:39:40 +0800 Subject: [PATCH] examples: add DRTIO sines --- .../sayma_drtio/repository/sines_drtio.py | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 artiq/examples/sayma_drtio/repository/sines_drtio.py diff --git a/artiq/examples/sayma_drtio/repository/sines_drtio.py b/artiq/examples/sayma_drtio/repository/sines_drtio.py new file mode 100644 index 000000000..b7c26bdcb --- /dev/null +++ b/artiq/examples/sayma_drtio/repository/sines_drtio.py @@ -0,0 +1,27 @@ +from artiq.experiment import * + + +class SAWGTestDRTIO(EnvExperiment): + def build(self): + self.setattr_device("core") + self.setattr_device("ttl_sma_out") + self.sawgs = [self.get_device("sawg"+str(8+i)) for i in range(8)] + + @kernel + def run(self): + core_log("waiting for DRTIO ready...") + while not self.core.get_drtio_link_status(0): + pass + core_log("OK") + + self.core.reset() + + for sawg in self.sawgs: + delay(1*ms) + sawg.amplitude1.set(.4) + # Do not use a sub-multiple of oscilloscope sample rates. + sawg.frequency0.set(9*MHz) + + while True: + delay(0.5*ms) + self.ttl_sma_out.pulse(0.5*ms)