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sayma_rtm: expose HMC SPI bus

This commit is contained in:
Sebastien Bourdeauducq 2017-08-26 16:31:31 -07:00
parent dbc12540da
commit 9194402ea5
1 changed files with 5 additions and 0 deletions
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5
artiq/gateware/targets/sayma_rtm.py
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@ -8,6 +8,7 @@ from migen.build.platforms.sinara import sayma_rtm
from misoc.interconnect import wishbone, stream from misoc.interconnect import wishbone, stream
from misoc.interconnect.csr import * from misoc.interconnect.csr import *
from misoc.cores import spi
from misoc.integration.wb_slaves import WishboneSlaveManager from misoc.integration.wb_slaves import WishboneSlaveManager
from misoc.integration.cpu_interface import get_csr_csv from misoc.integration.cpu_interface import get_csr_csv
@ -80,6 +81,10 @@ class SaymaRTM(Module):
self.submodules.rtm_identifier = RTMIdentifier() self.submodules.rtm_identifier = RTMIdentifier()
csr_devices.append("rtm_identifier") csr_devices.append("rtm_identifier")
self.submodules.converter_spi = spi.SPIMaster(platform.request("hmc_spi"))
csr_devices.append("converter_spi")
self.comb += platform.request("hmc7043_reset").eq(0)
# TODO: push all those serwb bits into library modules # TODO: push all those serwb bits into library modules
# maybe keep only 3 user-visible modules: serwb PLL, serwb PHY, and serwb core # maybe keep only 3 user-visible modules: serwb PLL, serwb PHY, and serwb core
# TODO: after this is done, stop exposing internal modules in serwb/__init__.py # TODO: after this is done, stop exposing internal modules in serwb/__init__.py