From 9194402ea5eb5f3c249cb37f3384a2e9f6d7318f Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 26 Aug 2017 16:31:31 -0700 Subject: [PATCH] sayma_rtm: expose HMC SPI bus --- artiq/gateware/targets/sayma_rtm.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index da38e8787..c9f1a0001 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -8,6 +8,7 @@ from migen.build.platforms.sinara import sayma_rtm from misoc.interconnect import wishbone, stream from misoc.interconnect.csr import * +from misoc.cores import spi from misoc.integration.wb_slaves import WishboneSlaveManager from misoc.integration.cpu_interface import get_csr_csv @@ -80,6 +81,10 @@ class SaymaRTM(Module): self.submodules.rtm_identifier = RTMIdentifier() csr_devices.append("rtm_identifier") + self.submodules.converter_spi = spi.SPIMaster(platform.request("hmc_spi")) + csr_devices.append("converter_spi") + self.comb += platform.request("hmc7043_reset").eq(0) + # TODO: push all those serwb bits into library modules # maybe keep only 3 user-visible modules: serwb PLL, serwb PHY, and serwb core # TODO: after this is done, stop exposing internal modules in serwb/__init__.py