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sayma_amc: set direction of external TTL buffer according to RTIO PHY OE

This commit is contained in:
Sebastien Bourdeauducq 2019-10-16 18:48:42 +08:00
parent 37d0a5dc19
commit 8fa3c6460e
1 changed files with 9 additions and 9 deletions
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18
artiq/gateware/targets/sayma_amc.py
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@ -248,13 +248,13 @@ class Satellite(SatelliteBase):
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
mcx_io = platform.request("mcx_io", 0) mcx_io = platform.request("mcx_io", 0)
self.comb += mcx_io.direction.eq(1) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
phy = ttl_serdes_ultrascale.Output(4, mcx_io.level) self.comb += mcx_io.direction.eq(phy.oe)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
mcx_io = platform.request("mcx_io", 1) mcx_io = platform.request("mcx_io", 1)
self.comb += mcx_io.direction.eq(0)
phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
self.comb += mcx_io.direction.eq(phy.oe)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
@ -306,13 +306,13 @@ class SimpleSatellite(SatelliteBase):
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
mcx_io = platform.request("mcx_io", 0) mcx_io = platform.request("mcx_io", 0)
self.comb += mcx_io.direction.eq(1) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
phy = ttl_serdes_ultrascale.Output(4, mcx_io.level) self.comb += mcx_io.direction.eq(phy.oe)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
mcx_io = platform.request("mcx_io", 1) mcx_io = platform.request("mcx_io", 1)
self.comb += mcx_io.direction.eq(0)
phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
self.comb += mcx_io.direction.eq(phy.oe)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
@ -424,13 +424,13 @@ class Master(MiniSoC, AMPSoC):
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
mcx_io = platform.request("mcx_io", 0) mcx_io = platform.request("mcx_io", 0)
self.comb += mcx_io.direction.eq(1) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
phy = ttl_serdes_ultrascale.Output(4, mcx_io.level) self.comb += mcx_io.direction.eq(phy.oe)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
mcx_io = platform.request("mcx_io", 1) mcx_io = platform.request("mcx_io", 1)
self.comb += mcx_io.direction.eq(0)
phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
self.comb += mcx_io.direction.eq(phy.oe)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))