From 8fa3c6460e12cffcb3f38ab734cd921288103400 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 16 Oct 2019 18:48:42 +0800 Subject: [PATCH] sayma_amc: set direction of external TTL buffer according to RTIO PHY OE --- artiq/gateware/targets/sayma_amc.py | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 44300653d..96e12faf3 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -248,13 +248,13 @@ class Satellite(SatelliteBase): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) mcx_io = platform.request("mcx_io", 0) - self.comb += mcx_io.direction.eq(1) - phy = ttl_serdes_ultrascale.Output(4, mcx_io.level) + phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level) + self.comb += mcx_io.direction.eq(phy.oe) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) mcx_io = platform.request("mcx_io", 1) - self.comb += mcx_io.direction.eq(0) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level) + self.comb += mcx_io.direction.eq(phy.oe) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) @@ -306,13 +306,13 @@ class SimpleSatellite(SatelliteBase): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) mcx_io = platform.request("mcx_io", 0) - self.comb += mcx_io.direction.eq(1) - phy = ttl_serdes_ultrascale.Output(4, mcx_io.level) + phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level) + self.comb += mcx_io.direction.eq(phy.oe) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) mcx_io = platform.request("mcx_io", 1) - self.comb += mcx_io.direction.eq(0) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level) + self.comb += mcx_io.direction.eq(phy.oe) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) @@ -424,13 +424,13 @@ class Master(MiniSoC, AMPSoC): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) mcx_io = platform.request("mcx_io", 0) - self.comb += mcx_io.direction.eq(1) - phy = ttl_serdes_ultrascale.Output(4, mcx_io.level) + phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level) + self.comb += mcx_io.direction.eq(phy.oe) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) mcx_io = platform.request("mcx_io", 1) - self.comb += mcx_io.direction.eq(0) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level) + self.comb += mcx_io.direction.eq(phy.oe) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy))