forked from M-Labs/artiq
drtio: update test
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7cd27abaa6
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8b736ddbc9
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@ -40,8 +40,9 @@ class DUT(Module):
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self.ttl0 = Signal()
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self.ttl1 = Signal()
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self.transceivers = DummyTransceiverPair(nwords)
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self.submodules.master = DRTIOMaster(self.transceivers.alice)
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self.submodules.master_ki = rtio.KernelInitiator(self.master.cri)
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rx_synchronizer = DummyRXSynchronizer()
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self.submodules.phy0 = ttl_simple.Output(self.ttl0)
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@ -59,7 +60,7 @@ class TestFullStack(unittest.TestCase):
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def test_controller(self):
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dut = DUT(2)
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kcsrs = dut.master.rt_controller.kcsrs
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kcsrs = dut.master_ki
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csrs = dut.master.rt_controller.csrs
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mgr = dut.master.rt_manager
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@ -160,7 +161,7 @@ class TestFullStack(unittest.TestCase):
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self.assertEqual(wlen, 2)
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def test_tsc_error():
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err_present = yield from mgr.err_present.read()
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err_present = yield from mgr.packet_err_present.read()
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self.assertEqual(err_present, 0)
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yield from csrs.tsc_correction.write(10000000)
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yield from csrs.set_time.write(1)
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@ -170,17 +171,17 @@ class TestFullStack(unittest.TestCase):
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yield from write(0, 1)
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for i in range(10):
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yield
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err_present = yield from mgr.err_present.read()
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err_code = yield from mgr.err_code.read()
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err_present = yield from mgr.packet_err_present.read()
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err_code = yield from mgr.packet_err_code.read()
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self.assertEqual(err_present, 1)
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self.assertEqual(err_code, 3)
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yield from mgr.err_present.write(1)
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yield from mgr.packet_err_present.write(1)
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yield
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err_present = yield from mgr.err_present.read()
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err_present = yield from mgr.packet_err_present.read()
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self.assertEqual(err_present, 0)
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def test():
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while not (yield dut.master.link_layer.ready):
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while not (yield from dut.master.link_layer.link_status.read()):
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yield
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yield from test_init()
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@ -214,7 +215,7 @@ class TestFullStack(unittest.TestCase):
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mgr = dut.master.rt_manager
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def test():
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while not (yield dut.master.link_layer.ready):
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while not (yield from dut.master.link_layer.link_status.read()):
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yield
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yield from mgr.update_packet_cnt.write(1)
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