forked from M-Labs/artiq
drtio: do not reset remote TSC on reset command
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0d5f962d0c
commit
7cd27abaa6
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@ -27,8 +27,8 @@ class DRTIOSatellite(Module):
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self.submodules.rt_packets = ClockDomainsRenamer("rtio")(
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rt_packets.RTPacketSatellite(link_layer_sync))
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self.submodules.iot = ClockDomainsRenamer("rio")(
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iot.IOT(self.rt_packets, channels, fine_ts_width, full_ts_width))
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self.submodules.iot = iot.IOT(
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self.rt_packets, channels, fine_ts_width, full_ts_width)
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self.clock_domains.cd_rio = ClockDomain()
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self.clock_domains.cd_rio_phy = ClockDomain()
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@ -8,7 +8,7 @@ from artiq.gateware.rtio import rtlink
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class IOT(Module):
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def __init__(self, rt_packets, channels, max_fine_ts_width, full_ts_width):
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tsc = Signal(full_ts_width - max_fine_ts_width)
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self.sync += \
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self.sync.rtio += \
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If(rt_packets.tsc_load,
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tsc.eq(rt_packets.tsc_value)
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).Else(
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@ -30,7 +30,8 @@ class IOT(Module):
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ev_layout.append(("address", address_width))
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ev_layout.append(("timestamp", len(tsc) + fine_ts_width))
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fifo = SyncFIFOBuffered(layout_len(ev_layout), channel.ofifo_depth)
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fifo = ClockDomainsRenamer("rio")(
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SyncFIFOBuffered(layout_len(ev_layout), channel.ofifo_depth))
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self.submodules += fifo
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fifo_in = Record(ev_layout)
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fifo_out = Record(ev_layout)
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@ -40,7 +41,7 @@ class IOT(Module):
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]
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# FIFO level
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self.sync += \
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self.sync.rio += \
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If(rt_packets.fifo_space_update &
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(rt_packets.fifo_space_channel == n),
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rt_packets.fifo_space.eq(channel.ofifo_depth - fifo.level))
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@ -48,7 +49,7 @@ class IOT(Module):
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# FIFO write
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self.comb += fifo.we.eq(rt_packets.write_stb
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& (rt_packets.write_channel == n))
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self.sync += [
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self.sync.rio += [
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If(rt_packets.write_overflow_ack,
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rt_packets.write_overflow.eq(0)),
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If(rt_packets.write_underflow_ack,
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@ -68,7 +69,7 @@ class IOT(Module):
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rt_packets.write_timestamp[max_fine_ts_width-fine_ts_width:])
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# FIFO read
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self.sync += [
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self.sync.rio += [
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fifo.re.eq(0),
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interface.stb.eq(0),
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If(fifo.readable &
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@ -78,8 +79,8 @@ class IOT(Module):
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)
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]
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if data_width:
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self.sync += interface.data.eq(fifo_out.data)
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self.sync.rio += interface.data.eq(fifo_out.data)
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if address_width:
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self.sync += interface.address.eq(fifo_out.address)
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self.sync.rio += interface.address.eq(fifo_out.address)
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if fine_ts_width:
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self.sync += interface.fine_ts.eq(fifo_out.timestamp[:fine_ts_width])
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self.sync.rio += interface.fine_ts.eq(fifo_out.timestamp[:fine_ts_width])
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