forked from M-Labs/artiq
ad9910: disable sync_clk output
Signed-off-by: Robert Jördens <rj@quartiq.de>
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@ -150,7 +150,7 @@ class AD9910:
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raise ValueError("Urukul AD9910 AUX_DAC mismatch")
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delay(50*us) # slack
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# Configure PLL settings and bring up PLL
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self.write32(_AD9910_REG_CFR2, 0x01400020)
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self.write32(_AD9910_REG_CFR2, 0x01000020)
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self.cpld.io_update.pulse(1*us)
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cfr3 = (0x0807c100 | (self.pll_vco << 24) |
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(self.pll_cp << 19) | (self.pll_n << 1))
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@ -265,9 +265,9 @@ class AD9910:
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(preset << 18) | # SYNC preset
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(0 << 11) | # SYNC output delay
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(in_delay << 3)) # SYNC receiver delay
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self.write32(_AD9910_REG_CFR2, 0x01400020) # clear SMP_ERR
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self.write32(_AD9910_REG_CFR2, 0x01000020) # clear SMP_ERR
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self.cpld.io_update.pulse(1*us)
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self.write32(_AD9910_REG_CFR2, 0x01400000) # enable SMP_ERR
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self.write32(_AD9910_REG_CFR2, 0x01000000) # enable SMP_ERR
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self.cpld.io_update.pulse(1*us)
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@kernel
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