From 8a47a6b2fb2c32fb7a9f585068f371205fe99a61 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Fri, 26 Oct 2018 10:25:23 +0000 Subject: [PATCH] ad9910: disable sync_clk output MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Robert Jördens --- artiq/coredevice/ad9910.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py index 0ac288d07..b2a05f813 100644 --- a/artiq/coredevice/ad9910.py +++ b/artiq/coredevice/ad9910.py @@ -150,7 +150,7 @@ class AD9910: raise ValueError("Urukul AD9910 AUX_DAC mismatch") delay(50*us) # slack # Configure PLL settings and bring up PLL - self.write32(_AD9910_REG_CFR2, 0x01400020) + self.write32(_AD9910_REG_CFR2, 0x01000020) self.cpld.io_update.pulse(1*us) cfr3 = (0x0807c100 | (self.pll_vco << 24) | (self.pll_cp << 19) | (self.pll_n << 1)) @@ -265,9 +265,9 @@ class AD9910: (preset << 18) | # SYNC preset (0 << 11) | # SYNC output delay (in_delay << 3)) # SYNC receiver delay - self.write32(_AD9910_REG_CFR2, 0x01400020) # clear SMP_ERR + self.write32(_AD9910_REG_CFR2, 0x01000020) # clear SMP_ERR self.cpld.io_update.pulse(1*us) - self.write32(_AD9910_REG_CFR2, 0x01400000) # enable SMP_ERR + self.write32(_AD9910_REG_CFR2, 0x01000000) # enable SMP_ERR self.cpld.io_update.pulse(1*us) @kernel