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drtio/transceiver/gtp_7series_init: remove dead code

This commit is contained in:
Florent Kermarrec 2018-02-19 10:02:23 +01:00
parent 782051f474
commit 89a158c0c9
2 changed files with 1 additions and 11 deletions
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3
artiq/gateware/drtio/transceiver/gtp_7series.py
View File

@ -39,8 +39,7 @@ class GTPSingle(Module):
self.comb += [
tx_init.stable_clkin.eq(self.stable_clkin),
qpll_channel.reset.eq(tx_init.pllreset),
tx_init.plllock.eq(qpll_channel.lock),
rx_init.plllock.eq(qpll_channel.lock),
tx_init.plllock.eq(qpll_channel.lock)
]
txdata = Signal(20)

9
artiq/gateware/drtio/transceiver/gtp_7series_init.py
View File

@ -146,7 +146,6 @@ class GTPRXInit(Module):
self.restart = Signal()
# GTP signals
self.plllock = Signal()
self.gtrxreset = Signal()
self.gtrxreset.attr.add("no_retiming")
self.gtrxpd = Signal()
@ -185,12 +184,10 @@ class GTPRXInit(Module):
self.sync += rxpmaresetdone_r.eq(rxpmaresetdone)
# Double-latch transceiver asynch outputs
plllock = Signal()
rxresetdone = Signal()
rxdlysresetdone = Signal()
rxsyncdone = Signal()
self.specials += [
MultiReg(self.plllock, plllock),
MultiReg(self.rxresetdone, rxresetdone),
MultiReg(self.rxdlysresetdone, rxdlysresetdone),
MultiReg(self.rxsyncdone, rxsyncdone)
@ -212,12 +209,6 @@ class GTPRXInit(Module):
self.rxuserrdy.eq(rxuserrdy)
]
# After configuration, transceiver resets have to stay low for
# at least 500ns (see AR43482)
pll_reset_cycles = ceil(500e-9*sys_clk_freq)
pll_reset_timer = WaitTimer(pll_reset_cycles)
self.submodules += pll_reset_timer
startup_fsm = ResetInserter()(FSM(reset_state="GTP_PD"))
self.submodules += startup_fsm