From 89a158c0c91a98a8de698af2f0ff83ef242aa9a3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 19 Feb 2018 10:02:23 +0100 Subject: [PATCH] drtio/transceiver/gtp_7series_init: remove dead code --- artiq/gateware/drtio/transceiver/gtp_7series.py | 3 +-- artiq/gateware/drtio/transceiver/gtp_7series_init.py | 9 --------- 2 files changed, 1 insertion(+), 11 deletions(-) diff --git a/artiq/gateware/drtio/transceiver/gtp_7series.py b/artiq/gateware/drtio/transceiver/gtp_7series.py index 4ed906391..397235e28 100644 --- a/artiq/gateware/drtio/transceiver/gtp_7series.py +++ b/artiq/gateware/drtio/transceiver/gtp_7series.py @@ -39,8 +39,7 @@ class GTPSingle(Module): self.comb += [ tx_init.stable_clkin.eq(self.stable_clkin), qpll_channel.reset.eq(tx_init.pllreset), - tx_init.plllock.eq(qpll_channel.lock), - rx_init.plllock.eq(qpll_channel.lock), + tx_init.plllock.eq(qpll_channel.lock) ] txdata = Signal(20) diff --git a/artiq/gateware/drtio/transceiver/gtp_7series_init.py b/artiq/gateware/drtio/transceiver/gtp_7series_init.py index 6c3f6ba99..ad4b0a456 100644 --- a/artiq/gateware/drtio/transceiver/gtp_7series_init.py +++ b/artiq/gateware/drtio/transceiver/gtp_7series_init.py @@ -146,7 +146,6 @@ class GTPRXInit(Module): self.restart = Signal() # GTP signals - self.plllock = Signal() self.gtrxreset = Signal() self.gtrxreset.attr.add("no_retiming") self.gtrxpd = Signal() @@ -185,12 +184,10 @@ class GTPRXInit(Module): self.sync += rxpmaresetdone_r.eq(rxpmaresetdone) # Double-latch transceiver asynch outputs - plllock = Signal() rxresetdone = Signal() rxdlysresetdone = Signal() rxsyncdone = Signal() self.specials += [ - MultiReg(self.plllock, plllock), MultiReg(self.rxresetdone, rxresetdone), MultiReg(self.rxdlysresetdone, rxdlysresetdone), MultiReg(self.rxsyncdone, rxsyncdone) @@ -212,12 +209,6 @@ class GTPRXInit(Module): self.rxuserrdy.eq(rxuserrdy) ] - # After configuration, transceiver resets have to stay low for - # at least 500ns (see AR43482) - pll_reset_cycles = ceil(500e-9*sys_clk_freq) - pll_reset_timer = WaitTimer(pll_reset_cycles) - self.submodules += pll_reset_timer - startup_fsm = ResetInserter()(FSM(reset_state="GTP_PD")) self.submodules += startup_fsm