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Firmware: Set DACs RETIMER-CLK to Phase 1 Shuttler 

- Intend to maintain the same pipeline latency across all DACs on Shuttler
- Force the RETIMER-CLK to be PHASE 1 on all DACs
- See Issue #2200 for details
This commit is contained in:
linuswck 2023-09-12 11:54:40 +08:00 committed by Sébastien Bourdeauducq
parent 9e5b62a6b1
commit 85abb1da2c
1 changed files with 6 additions and 0 deletions
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6
artiq/firmware/libboard_artiq/ad9117.rs
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@ -7,6 +7,8 @@ const QRCML_REG : u8 = 0x08;
const CLKMODE_REG : u8 = 0x14; const CLKMODE_REG : u8 = 0x14;
const VERSION_REG : u8 = 0x1F; const VERSION_REG : u8 = 0x1F;
const RETIMER_CLK_PHASE : u8 = 0b11;
fn hard_reset() { fn hard_reset() {
unsafe { unsafe {
// Min Pulse Width: 50ns // Min Pulse Width: 50ns
@ -57,6 +59,10 @@ pub fn init() -> Result<(), &'static str> {
return Err("DAC AD9117 retiming failure"); return Err("DAC AD9117 retiming failure");
} }
// Force RETIMER-CLK to be Phase 1 as DCLKIO and CLKIN is known to be safe at Phase 1
// See Issue #2200
write(channel, CLKMODE_REG, RETIMER_CLK_PHASE << 6 | 1 << 2 | RETIMER_CLK_PHASE)?;
// Set the DACs input data format to be twos complement // Set the DACs input data format to be twos complement
// Set IFIRST and IRISING to True // Set IFIRST and IRISING to True
write(channel, DATA_CTRL_REG, 1 << 7 | 1 << 5 | 1 << 4)?; write(channel, DATA_CTRL_REG, 1 << 7 | 1 << 5 | 1 << 4)?;