From 85abb1da2c7a787116d68b2a0e0a472fc9cf6de4 Mon Sep 17 00:00:00 2001 From: linuswck Date: Tue, 12 Sep 2023 11:54:40 +0800 Subject: [PATCH] Firmware: Set DACs RETIMER-CLK to Phase 1 Shuttler - Intend to maintain the same pipeline latency across all DACs on Shuttler - Force the RETIMER-CLK to be PHASE 1 on all DACs - See Issue #2200 for details --- artiq/firmware/libboard_artiq/ad9117.rs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/artiq/firmware/libboard_artiq/ad9117.rs b/artiq/firmware/libboard_artiq/ad9117.rs index 4c152e976..5aafb2ace 100644 --- a/artiq/firmware/libboard_artiq/ad9117.rs +++ b/artiq/firmware/libboard_artiq/ad9117.rs @@ -7,6 +7,8 @@ const QRCML_REG : u8 = 0x08; const CLKMODE_REG : u8 = 0x14; const VERSION_REG : u8 = 0x1F; +const RETIMER_CLK_PHASE : u8 = 0b11; + fn hard_reset() { unsafe { // Min Pulse Width: 50ns @@ -57,6 +59,10 @@ pub fn init() -> Result<(), &'static str> { return Err("DAC AD9117 retiming failure"); } + // Force RETIMER-CLK to be Phase 1 as DCLKIO and CLKIN is known to be safe at Phase 1 + // See Issue #2200 + write(channel, CLKMODE_REG, RETIMER_CLK_PHASE << 6 | 1 << 2 | RETIMER_CLK_PHASE)?; + // Set the DACs input data format to be twos complement // Set IFIRST and IRISING to True write(channel, DATA_CTRL_REG, 1 << 7 | 1 << 5 | 1 << 4)?;