forked from M-Labs/artiq
Firmware: Set DACs RETIMER-CLK to Phase 1 Shuttler
- Intend to maintain the same pipeline latency across all DACs on Shuttler - Force the RETIMER-CLK to be PHASE 1 on all DACs - See Issue #2200 for details
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@ -7,6 +7,8 @@ const QRCML_REG : u8 = 0x08;
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const CLKMODE_REG : u8 = 0x14;
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const CLKMODE_REG : u8 = 0x14;
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const VERSION_REG : u8 = 0x1F;
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const VERSION_REG : u8 = 0x1F;
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const RETIMER_CLK_PHASE : u8 = 0b11;
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fn hard_reset() {
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fn hard_reset() {
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unsafe {
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unsafe {
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// Min Pulse Width: 50ns
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// Min Pulse Width: 50ns
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@ -57,6 +59,10 @@ pub fn init() -> Result<(), &'static str> {
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return Err("DAC AD9117 retiming failure");
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return Err("DAC AD9117 retiming failure");
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}
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}
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// Force RETIMER-CLK to be Phase 1 as DCLKIO and CLKIN is known to be safe at Phase 1
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// See Issue #2200
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write(channel, CLKMODE_REG, RETIMER_CLK_PHASE << 6 | 1 << 2 | RETIMER_CLK_PHASE)?;
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// Set the DACs input data format to be twos complement
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// Set the DACs input data format to be twos complement
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// Set IFIRST and IRISING to True
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// Set IFIRST and IRISING to True
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write(channel, DATA_CTRL_REG, 1 << 7 | 1 << 5 | 1 << 4)?;
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write(channel, DATA_CTRL_REG, 1 << 7 | 1 << 5 | 1 << 4)?;
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