forked from M-Labs/artiq
drtio: large data support
This commit is contained in:
parent
8b736ddbc9
commit
8090abef5d
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@ -29,8 +29,20 @@ class PacketLayoutManager:
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layout.append(("packet_pad", self.alignment - misalignment))
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self.layouts[name] = layout
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def field_length(self, type_name, field_name):
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layout = self.layouts[type_name]
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for name, length in layout:
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if name == field_name:
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return length
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raise KeyError
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def get_m2s_layouts(alignment):
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if alignment > 128:
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short_data_len = alignment - 128 + 16
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else:
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short_data_len = 16
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plm = PacketLayoutManager(alignment)
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plm.add_type("echo_request")
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plm.add_type("set_time", ("timestamp", 64))
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@ -38,8 +50,8 @@ def get_m2s_layouts(alignment):
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plm.add_type("write", ("timestamp", 64),
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("channel", 16),
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("address", 16),
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("data_len", 8),
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("short_data", 8))
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("extra_data_cnt", 8),
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("short_data", short_data_len))
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plm.add_type("fifo_space_request", ("channel", 16))
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return plm
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@ -125,34 +137,33 @@ class TransmitDatapath(Module):
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self.ws = ws
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self.plm = plm
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# inputs
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self.packet_buffer = Signal(max(layout_len(l)
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for l in plm.layouts.values()))
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w_in_packet = len(self.packet_buffer)//ws
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self.packet_len = Signal(max=w_in_packet+1)
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self.packet_last_n = Signal(max=w_in_packet)
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self.packet_stb = Signal()
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self.packet_last = Signal()
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# control
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self.stb = Signal()
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self.done = Signal()
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self.raw_stb = Signal()
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self.raw_data = Signal(ws)
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# # #
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packet_buffer_count = Signal(max=w_in_packet+1)
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packet_buffer_count = Signal(max=w_in_packet)
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self.comb += self.packet_last.eq(packet_buffer_count == self.packet_last_n)
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self.sync += [
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self.done.eq(0),
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frame.eq(0),
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packet_buffer_count.eq(0),
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If(self.stb & ~self.done,
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If(packet_buffer_count == self.packet_len,
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self.done.eq(1)
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).Else(
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frame.eq(1),
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Case(packet_buffer_count,
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{i: data.eq(self.packet_buffer[i*ws:(i+1)*ws])
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for i in range(w_in_packet)}),
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packet_buffer_count.eq(packet_buffer_count + 1)
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)
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If(self.packet_stb,
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frame.eq(1),
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Case(packet_buffer_count,
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{i: data.eq(self.packet_buffer[i*ws:(i+1)*ws])
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for i in range(w_in_packet)}),
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packet_buffer_count.eq(packet_buffer_count + 1)
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),
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If(self.raw_stb,
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frame.eq(1),
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data.eq(self.raw_data)
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)
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]
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@ -170,8 +181,9 @@ class TransmitDatapath(Module):
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if kwargs:
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raise ValueError
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return [
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self.packet_stb.eq(1),
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self.packet_buffer.eq(value),
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self.packet_len.eq(idx//self.ws)
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self.packet_last_n.eq(idx//self.ws-1)
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]
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@ -191,7 +203,7 @@ class RTPacketSatellite(Module):
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self.write_timestamp = Signal(64)
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self.write_channel = Signal(16)
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self.write_address = Signal(16)
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self.write_data = Signal(256)
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self.write_data = Signal(512)
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self.write_overflow = Signal()
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self.write_overflow_ack = Signal()
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self.write_underflow = Signal()
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@ -212,6 +224,20 @@ class RTPacketSatellite(Module):
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link_layer.tx_rt_frame, link_layer.tx_rt_data, tx_plm)
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self.submodules += tx_dp
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# RX write data buffer
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write_data_buffer_load = Signal()
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write_data_buffer_cnt = Signal(max=512//ws+1)
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write_data_buffer = Signal(512)
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self.sync += \
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If(write_data_buffer_load,
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Case(write_data_buffer_cnt,
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{i: write_data_buffer[i*ws:(i+1)*ws].eq(link_layer.rx_rt_data)
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for i in range(512//ws)}),
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write_data_buffer_cnt.eq(write_data_buffer_cnt + 1)
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).Else(
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write_data_buffer_cnt.eq(0)
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)
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# RX->TX
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echo_req = Signal()
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err_set = Signal()
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@ -241,7 +267,7 @@ class RTPacketSatellite(Module):
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self.write_address.eq(
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rx_dp.packet_as["write"].address),
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self.write_data.eq(
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rx_dp.packet_as["write"].short_data)
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Cat(rx_dp.packet_as["write"].short_data, write_data_buffer))
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]
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reset = Signal()
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@ -287,8 +313,11 @@ class RTPacketSatellite(Module):
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NextState("INPUT")
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)
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rx_fsm.act("WRITE",
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self.write_stb.eq(1),
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NextState("INPUT")
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write_data_buffer_load.eq(1),
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If(write_data_buffer_cnt == rx_dp.packet_as["write"].extra_data_cnt,
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self.write_stb.eq(1),
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NextState("INPUT")
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)
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)
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rx_fsm.act("FIFO_SPACE",
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fifo_space_set.eq(1),
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@ -309,32 +338,27 @@ class RTPacketSatellite(Module):
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)
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tx_fsm.act("ECHO",
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tx_dp.send("echo_reply"),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("IDLE"))
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If(tx_dp.packet_last, NextState("IDLE"))
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)
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tx_fsm.act("FIFO_SPACE",
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fifo_space_ack.eq(1),
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tx_dp.send("fifo_space_reply", space=self.fifo_space),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("IDLE"))
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If(tx_dp.packet_last, NextState("IDLE"))
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)
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tx_fsm.act("ERROR_WRITE_OVERFLOW",
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self.write_overflow_ack.eq(1),
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tx_dp.send("error", code=error_codes["write_overflow"]),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("IDLE"))
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If(tx_dp.packet_last, NextState("IDLE"))
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)
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tx_fsm.act("ERROR_WRITE_UNDERFLOW",
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self.write_underflow_ack.eq(1),
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tx_dp.send("error", code=error_codes["write_underflow"]),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("IDLE"))
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If(tx_dp.packet_last, NextState("IDLE"))
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)
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tx_fsm.act("ERROR",
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err_ack.eq(1),
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tx_dp.send("error", code=err_code),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("IDLE"))
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If(tx_dp.packet_last, NextState("IDLE"))
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)
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@ -399,7 +423,7 @@ class RTPacketMaster(Module):
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self.write_timestamp = Signal(64)
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self.write_channel = Signal(16)
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self.write_address = Signal(16)
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self.write_data = Signal(256)
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self.write_data = Signal(512)
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# fifo space interface
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# write with timestamp[48:] == 0xffff to make a fifo space request
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@ -437,23 +461,83 @@ class RTPacketMaster(Module):
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# # #
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# CDC
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# RX/TX datapath
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assert len(link_layer.tx_rt_data) == len(link_layer.rx_rt_data)
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assert len(link_layer.tx_rt_data) % 8 == 0
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ws = len(link_layer.tx_rt_data)
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tx_plm = get_m2s_layouts(ws)
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tx_dp = ClockDomainsRenamer("rtio")(TransmitDatapath(
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link_layer.tx_rt_frame, link_layer.tx_rt_data, tx_plm))
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self.submodules += tx_dp
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rx_plm = get_s2m_layouts(ws)
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rx_dp = ClockDomainsRenamer("rtio_rx")(ReceiveDatapath(
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link_layer.rx_rt_frame, link_layer.rx_rt_data, rx_plm))
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self.submodules += rx_dp
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# Write FIFO and extra data count
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wfifo = ClockDomainsRenamer({"write": "sys", "read": "rtio"})(
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AsyncFIFO(64+16+16+256, write_fifo_depth))
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AsyncFIFO(64+16+16+512, write_fifo_depth))
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self.submodules += wfifo
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write_timestamp = Signal(64)
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write_channel = Signal(16)
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write_address = Signal(16)
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write_data = Signal(256)
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write_timestamp_d = Signal(64)
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write_channel_d = Signal(16)
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write_address_d = Signal(16)
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write_data_d = Signal(512)
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self.comb += [
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wfifo.we.eq(self.write_stb),
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self.write_ack.eq(wfifo.writable),
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wfifo.din.eq(Cat(self.write_timestamp, self.write_channel,
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self.write_address, self.write_data)),
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Cat(write_timestamp, write_channel,
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write_address, write_data).eq(wfifo.dout)
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Cat(write_timestamp_d, write_channel_d,
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write_address_d, write_data_d).eq(wfifo.dout)
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]
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wfb_readable = Signal()
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wfb_re = Signal()
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self.comb += wfifo.re.eq(wfifo.readable & (~wfb_readable | wfb_re))
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self.sync.rtio += \
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If(wfifo.re,
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wfb_readable.eq(1),
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).Elif(wfb_re,
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wfb_readable.eq(0),
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)
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write_timestamp = Signal(64)
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write_channel = Signal(16)
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write_address = Signal(16)
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write_extra_data_cnt = Signal(8)
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write_data = Signal(512)
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self.sync.rtio += If(wfifo.re,
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write_timestamp.eq(write_timestamp_d),
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write_channel.eq(write_channel_d),
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write_address.eq(write_address_d),
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write_data.eq(write_data_d))
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short_data_len = tx_plm.field_length("write", "short_data")
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write_extra_data = Signal(512)
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self.comb += write_extra_data.eq(write_data[short_data_len:])
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for i in range(512//ws):
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self.sync.rtio += If(wfifo.re,
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If(write_extra_data[ws*i:ws*(i+1)] != 0, write_extra_data_cnt.eq(i+1)))
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extra_data_ce = Signal()
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extra_data_last = Signal()
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extra_data_counter = Signal(max=512//ws+1)
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self.comb += [
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Case(extra_data_counter,
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{i+1: tx_dp.raw_data.eq(write_extra_data[i*ws:(i+1)*ws])
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for i in range(512//ws)}),
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extra_data_last.eq(extra_data_counter == write_extra_data_cnt)
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]
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self.sync.rtio += \
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If(extra_data_ce,
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extra_data_counter.eq(extra_data_counter + 1),
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).Else(
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extra_data_counter.eq(1)
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)
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# CDC
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fifo_space_not = Signal()
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fifo_space = Signal(16)
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self.submodules += _CrossDomainNotification("rtio_rx",
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@ -485,21 +569,8 @@ class RTPacketMaster(Module):
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error_not, error_code,
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self.error_not, self.error_not_ack, self.error_code)
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# RX/TX datapath
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assert len(link_layer.tx_rt_data) == len(link_layer.rx_rt_data)
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assert len(link_layer.tx_rt_data) % 8 == 0
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ws = len(link_layer.tx_rt_data)
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tx_plm = get_m2s_layouts(ws)
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tx_dp = ClockDomainsRenamer("rtio")(TransmitDatapath(
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link_layer.tx_rt_frame, link_layer.tx_rt_data, tx_plm))
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self.submodules += tx_dp
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rx_plm = get_s2m_layouts(ws)
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rx_dp = ClockDomainsRenamer("rtio_rx")(ReceiveDatapath(
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link_layer.rx_rt_frame, link_layer.rx_rt_data, rx_plm))
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self.submodules += rx_dp
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# TX FSM
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tx_fsm = ClockDomainsRenamer("rtio")(FSM(reset_state="IDLE_WRITE"))
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tx_fsm = ClockDomainsRenamer("rtio")(FSM(reset_state="IDLE"))
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self.submodules += tx_fsm
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echo_sent_now = Signal()
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@ -508,18 +579,12 @@ class RTPacketMaster(Module):
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tsc_value_load = Signal()
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self.sync.rtio += If(tsc_value_load, tsc_value.eq(self.tsc_value))
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tx_fsm.act("IDLE_WRITE",
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tx_dp.send("write",
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timestamp=write_timestamp,
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channel=write_channel,
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address=write_address,
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short_data=write_data),
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If(wfifo.readable,
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tx_fsm.act("IDLE",
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If(wfb_readable,
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If(write_timestamp[48:] == 0xffff,
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NextState("FIFO_SPACE")
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).Else(
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tx_dp.stb.eq(1),
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wfifo.re.eq(tx_dp.done)
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NextState("WRITE")
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)
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).Else(
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If(echo_stb,
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@ -533,36 +598,56 @@ class RTPacketMaster(Module):
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)
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)
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)
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tx_fsm.act("WRITE",
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tx_dp.send("write",
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timestamp=write_timestamp,
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channel=write_channel,
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address=write_address,
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extra_data_cnt=write_extra_data_cnt,
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short_data=write_data[:short_data_len]),
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If(tx_dp.packet_last,
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If(write_extra_data_cnt == 0,
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wfb_re.eq(1),
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NextState("IDLE")
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).Else(
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NextState("WRITE_EXTRA")
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)
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)
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)
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tx_fsm.act("WRITE_EXTRA",
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tx_dp.raw_stb.eq(1),
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extra_data_ce.eq(1),
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If(extra_data_last,
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wfb_re.eq(1),
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NextState("IDLE")
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)
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)
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tx_fsm.act("FIFO_SPACE",
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tx_dp.send("fifo_space_request", channel=write_channel),
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tx_dp.stb.eq(1),
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If(tx_dp.done,
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wfifo.re.eq(1),
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NextState("IDLE_WRITE")
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If(tx_dp.packet_last,
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wfb_re.eq(1),
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NextState("IDLE")
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)
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)
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tx_fsm.act("ECHO",
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tx_dp.send("echo_request"),
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tx_dp.stb.eq(1),
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If(tx_dp.done,
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If(tx_dp.packet_last,
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echo_ack.eq(1),
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NextState("IDLE_WRITE")
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NextState("IDLE")
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)
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)
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tx_fsm.act("SET_TIME",
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tx_dp.send("set_time", timestamp=tsc_value),
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tx_dp.stb.eq(1),
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If(tx_dp.done,
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If(tx_dp.packet_last,
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set_time_ack.eq(1),
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NextState("IDLE_WRITE")
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NextState("IDLE")
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)
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)
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tx_fsm.act("RESET",
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tx_dp.send("reset", phy=reset_phy),
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tx_dp.stb.eq(1),
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If(tx_dp.done,
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If(tx_dp.packet_last,
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reset_ack.eq(1),
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NextState("IDLE_WRITE")
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NextState("IDLE")
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)
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)
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