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kc705.clock: add all spi buses

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This commit is contained in:
Robert Jördens 2016-03-04 00:03:48 +01:00
parent 669fbaa4f1
commit 7ff0c89d51
1 changed files with 1 additions and 1 deletions
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2
artiq/gateware/targets/kc705.py
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@ -264,7 +264,7 @@ class NIST_CLOCK(_NIST_Ions):
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=4, ififo_depth=4))
for i in range(1): # spi1 and spi2 collide in pinout with ttl
for i in range(3):
phy = spi.SPIMaster(self.platform.request("spi", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(